DATA SHEET
DS07-12610-3E
8-bit Microcontrollers
CMOS
FMC-8FX MB95120MB series
2
MB95128MB/F124MB/F124NB/F124JB/F126MB/F126NB/MB95F126JB/F128MB/F128NB/F128JB/FV100D-103
■DESCRIPTION
The MB95120MB series is general-purpose, single-chip microcontrollers. In addition to a compact instruction set,the microcontrollers contain a variety of peripheral functions. Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■FEATURE
• F2MC-8FX CPU core
Instruction set optimized for controllers•Multiplication and division instructions•16-bit arithmetic operations•Bit test branch instruction
•Bit manipulation instructions etc.• Clock
•Main clock
•Main PLL clock•Sub clock
•Sub PLL clock • Timer
•8/16-bit compound timer × 2 channels
• Can be used to interval timer, PWC timer, PWM timer and input capture.•16-bit reload timer × 1 channel•8/16-bit PPG × 2 channels•16-bit PPG × 2 channels
(Continued)
Be sure to refer to the “Check Sheet” for the latest cautions on development.
“Check Sheet” is seen at the following support page
URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system development.
Copyright©2006-2007 FUJITSU LIMITED All rights reserved
MB95120MB Series
(Continued)
•Timebase timer × 1 channel•Watch prescaler × 1 channel• LIN-UART × 1 channel
•LIN function, clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable•Full duplex double buffer• UART/SIO × 1 channel
•Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable•Full duplex double buffer2C* × 1 channel• I
•Built-in wake-up function• External interrupt × 12 channels
•Interrupt by edge detection (rising, falling, or both edges can be selected) •Can be used to recover from low-power consumption (standby) modes.• 8/10-bit A/D converter × 12 channels
•8-bit or 10-bit resolution can be selected• LCD controller (LCDC)
•40 SEG × 4 COM (Max 160 pixels) •With blinking function
• Low-power consumption (standby) mode•Stop mode•Sleep mode•Watch mode
•Timebase timer mode• I/O port
•The number of maximum ports : Max 87•Port configuration
•General-purpose I/O ports (N-ch open drain) : 2 ports•General-purpose I/O ports (CMOS) : 85 ports• Programmable input voltage levels of port
Automotive input level / CMOS input level / hysteresis input level• Dual operation Flash memory
•Erase/write and read can be executed in the different bank (Upper Bank/Lower Bank) at the same time.• Flash memory security function
Protects the content of Flash memory (Flash memory device only) * :
Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips.
2
MB95120MB Series
■MEMORY LINEUP
Flash memory
MB95F124MBMB95F124NBMB95F124JBMB95F126MBMB95F126NBMB95F126JBMB95F128MBMB95F128NBMB95F128JB
60 Kbytes
2 Kbytes
32 Kbytes
1 Kbyte
16 Kbytes
512 bytesRAM
3
MB95120MB Series
■PRODUCT LINEUP
Part number
MB95128MB
ParameterType
ROM capacity*1RAM capacity*1Reset outputOption*2Clock systemLow voltage detection resetClock supervisor
Yes/NoYes/No
No
No
Yes/NoMASK ROM product
MB95F124MBMB95F126MBMB95F128MB
MB95F124NBMB95F126NBMB95F128NBFlash memory product
60 Kbytes (Max) 2 Kbytes (Max)
YesDual clock
Yes
YesNoMB95F124JBMB95F126JBMB95F128JB
CPU functions
Number of basic instructions : 136Instruction bit length : 8 bitsInstruction length : 1 to 3 bytesData bit length : 1, 8, and 16 bits
Minimum instruction execution time : 61.5 ns (at machine clock frequency 16.25 MHz) Interrupt processing time : 0.6 µs (at machine clock frequency 16.25 MHz) General-purpose I/O port (N-ch open drain) : 2 portsGeneral-purpose I/O port (CMOS) : 85 portsProgrammable input voltage levels of port :
Automotive input level / CMOS input level / hysteresis input levelInterrupt cycle : 0.5 ms, 2.1 ms, 8.2 ms, 32.8 ms (at main oscillation clock 4 MHz) Reset generated cycle
At main oscillation clock 10 MHzAt sub oscillation clock 32.768 kHzCapable of replacing 3 bytes of ROM data
Master/slave sending and receiving
Bus error function and arbitration functionDetecting transmitting direction function
Start condition repeated generation and detection functionsBuilt-in wake-up function
Data transfer capable in UART/SIOFull duplex double buffer
Variable data length (5/6/7/8-bit), built-in baud rate generatorNRZ type transfer format, error detected functionLSB-first or MSB-first can be selected.
Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capableDedicated reload timer allowing a wide range of communication speeds to be set.Full duplex double buffer.
Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capableLIN functions available as the LIN master or LIN slave.
: Min 105 ms : Min 250 ms
Ports (Max 87 ports)Timebase timer(1 channel)Watchdog timerWild registerPeripheral functionsI2C
(1 channel)
UART/SIO(1 channel)
LIN-UART(1 channel)
8/10-bit A/D converter
8-bit or 10-bit resolution can be selected.
(12 channels)
(Continued)
4
MB95120MB Series
(Continued)
Part number
MB95128MB
Parameter
MB95F124MBMB95F126MBMB95F128MBMB95F124NBMB95F126NBMB95F128NBMB95F124JBMB95F126JBMB95F128JB
LCD controller (LCDC)
COM output : 4 (Max) SEG output : 40 (Max) LCD drive power supply (bias) pin : 4 (Max) 40 SEG × 4 COM : 160 pixels can be displayed.Duty LCD mode
Operable in LCD standby modeWith blinking function
Built-in division resistance for LCD drive
Two clock modes and two counter operating modes can be selected. Square waveform output
Count clock : 7 internal clocks and external clock can be selected.
Counter operating mode : reload mode or one-shot mode can be selected.
16-bit reload timer(1 channel)Peripheral functionsEach channel of the timer can be used as “8-bit timer × 2 channels” or “16-bit timer × 1 channel”.
8/16-bit compound
Built-in timer function, PWC function, PWM function, capture function and square
timer (2 channels)
waveform output
Count clock : 7 internal clocks and external clock can be selected.16-bit PPG(2 channels)8/16-bit PPG(2 channels)Watch counterWatch prescaler(1 channel)External interrupt(12 channels)
PWM mode or one-shot mode can be selected.
Counter operating clock : Eight selectable clock sourcesSupport for external trigger start
Each channel of the PPG can be used as “8-bit PPG × 2 channels” or “16-bit PPG × 1 channel”.
Counter operating clock : Eight selectable clock sources
Count clock : Four selectable clock sources (125 ms, 250 ms, 500 ms, or 1 s)
Counter value can be set from 0 to 63 (Capable of counting for 1 minute when selecting clock source 1 second and setting counter value to 60) .4 selectable interval times (125 ms, 250 ms, 500 ms, or 1 s)
Interrupt by edge detection (rising, falling, or both edges can be selected.) Can be used to recover from standby modes.
Supports automatic programming, Embedded AlgorithmTM *3Write/Erase/Erase-Suspend/Resume commandsA flag indicating completion of the algorithm
Number of write/erase cycles (Minimum) : 10000 timesData retention time : 20 years
Erase can be performed on each block
Block protection with external programming voltageDual operation Flash memory
Flash Security Feature for protecting the content of the FlashSleep, stop, watch, and timebase timer
Flash memory
Standby mode
*1 : For ROM capacitance and RAM capacitance, refer to “■ MEMORY LINEUP”.*2 : For details of option, refer to “■ MASK OPTION”.
*3 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.
Note : Part number of evaluation product in MB95120MB series is MB95FV100D-103. When using it, the MCU
board (MB2146-303A) is required.
5
MB95120MB Series
■OSCILLATION STABILIZATION WAIT TIME
The initial value of the main clock oscillation stabilization wait time is fixed to the maximum value. The maximumvalue is shown as follows.
Oscillation stabilization wait time
(214−2) /FCH
Remarks
Approx. 4.10 ms (at main oscillation clock 4 MHz)
■PACKAGES AND CORRESPONDING PRODUCTS
Part number
Package
FPT-100P-M20FPT-100P-M06BGA-224P-M08 : Available : Unavailable
MB95128MB
MB95F124MB/F124NB/F124JBMB95F126MB/F126NB/F126JBMB95F128MB/F128NB/F128JB
MB95FV100D-103
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MB95120MB Series
■DIFFERENCES AMONG PRODUCTS AND NOTES ON SELECTING PRODUCTS
• Notes on Using Evaluation Products
The Evaluation product has not only the functions of the MB95120MB series but also those of other productsto support software development for multiple series and models of the F2MC-8FX family. The I/O addresses forperipheral resources not used by the MB95120MB series are therefore access-barred. Read/write access tothese access-barred addresses may cause peripheral resources supposed to be unused to operate, resultingin unexpected malfunctions of hardware or software.
Particularly, do not use word access to odd numbered byte address in the prohibited areas (If these access areused, the address may be read or written unexpectedly).
Also, as the read values of prohibited addresses on the evaluation product are different to the values on theFlash memory and MASK ROM products, do not use these values in the program.
The Evaluation product do not support the functions of some bits in single-byte registers. Read/write access tothese bits does not cause hardware malfunctions. Since the Evaluation, Flash memory product, and MASK ROMproduct are designed to behave completely the same way in terms of hardware and software.• Difference of Memory Spaces
If the amount of memory on the Evaluation product is different from that of the Flash memory product or MASKROM product, carefully check the difference in the amount of memory from the model to be actually used whendeveloping software.
For details of memory space, refer to “■ CPU CORE”.
• Current Consumption
•The current consumption of Flash memory product is typically greater than for MASK ROM product.•For details of current consumption, refer to “■ ELECTRICAL CHARACTERISTICS”.• Package
For details of information on each package, refer to “■ PACKAGES AND CORRESPONDING PRODUCTS” and“■ PACKAGE DIMENSIONS”.• Operating voltage
The operating voltage are different between the Evaluation, Flash memory products, and MASK ROM product.For details of operating voltage, refer to “■ ELECTRICAL CHARACTERISTICS”.
7
MB95120MB Series
■PIN ASSIGNMENT(TOP VIEW)VCCP90/V3P91/V2P92/V1P93/V0P94P95PA0/COM0PA1/COM1PA2/COM2PA3/COM3PB0/SEG00PB1/SEG01PB2/SEG02PB3/SEG03PB4/SEG04PB5/SEG05PB6/SEG06PB7/SEG07PC0/SEG08PC1/SEG09PC2/SEG10PC3/SEG11PC4/SEG12VCC100999897969594939291908988878685848382818079787776VSSCP00/INT00P01/INT01P02/INT02P03/INT03P04/INT04P05/INT05P06/INT06P07/INT07P10/UI0P11/UO0P12/UCK0P13/TRG0/ADTGP14/PPG0P20/PPG00P21/PPG01P22/TO00P23/TO01P24/EC0P50/SCL0P51/SDA0P52/PPG1AVRAVCC1234567891011121314151617181920212223242575747372717069686766656463626160595857565554535251PC5/SEG13PC6/SEG14PC7/SEG15PD0/SEG16PD1/SEG17PD2/SEG18PD3/SEG19PD4/SEG20PD5/SEG21PD6/SEG22PD7/SEG23PE0/SEG24PE1/SEG25PE2/SEG26PE3/SEG27PE4/SEG28/INT10PE5/SEG29/INT11PE6/SEG30/INT12PE7/SEG31/INT13P60/SEG32/PPG10P61/SEG33/PPG11MODX0X1VSSLQFP-10026272829303132333435363738394041424344454647484950AVSSP30/AN00P31/AN01P32/AN02P33/AN03P34/AN04P35/AN05P36/AN06P37/AN07P40/AN08P41/AN09P42/AN10P43/AN11P53/TRG1P70/TO0P71/TI0P67/SEG39/SINP66/SEG38/SOTP65/SEG37/SCKP64/SEG36/EC1P63/SEG35/TO11P62/SEG34/TO10RSTX0AX1A (FPT-100P-M20) (Continued)
8
MB95120MB Series
(Continued)(TOP VIEW)10099989796959493929190898887868584838281P92/V1P93/V0P94P95PA0/COM0PA1/COM1PA2/COM2PA3/COM3PB0/SEG00PB1/SEG01PB2/SEG02PB3/SEG03PB4/SEG04PB5/SEG05PB6/SEG06PB7/SEG07PC0/SEG08PC1/SEG09PC2/SEG10PC3/SEG11P91/V2P90/V3VCCVSSCP00/INT00P01/INT01P02/INT02P03/INT03P04/INT04P05/INT05P06/INT06P07/INT07P10/UI0P11/UO0P12/UCK0P13/TRG0/ADTGP14/PPG0P20/PPG00P21/PPG01P22/TO00P23/TO01P24/EC0P50/SCL0P51/SDA0P52/PPG1AVRAVCCAVSSP30/AN00123456789101112131415161718192021222324252627282930QFP-100807978777675747372717069686766656463626160595857565554535251PC4/SEG12VCCPC5/SEG13PC6/SEG14PC7/SEG15PD0/SEG16PD1/SEG17PD2/SEG18PD3/SEG19PD4/SEG20PD5/SEG21PD6/SEG22PD7/SEG23PE0/SEG24PE1/SEG25PE2/SEG26PE3/SEG27PE4/SEG28/INT10PE5/SEG29/INT11PE6/SEG30/INT12PE7/SEG31/INT13P60/SEG32/PPG10P61/SEG33/PPG11MODX0X1VSSX1AX0ARST3132333435363738394041424344454647484950P31/AN01P32/AN02P33/AN03P34/AN04P35/AN05P36/AN06P37/AN07P40/AN08P41/AN09P42/AN10P43/AN11P53/TRG1P70/TO0P71/TI0P67/SEG39/SINP66/SEG38/SOTP65/SEG37/SCKP64/SEG36/EC1P63/SEG35/TO11P62/SEG34/TO10 (FPT-100P-M06) 9
MB95120MB Series
■PIN DESCRIPTION
Pin no.
LQFP *1
12345678910111213141516171819202122232425
QFP *2
45678910111213141516171819202122232425262728
Pin nameVSSCP00/INT00P01/INT01P02/INT02P03/INT03P04/INT04P05/INT05P06/INT06P07/INT07P10/UI0P11/UO0P12/UCK0P13/TRG0/ADTGP14/PPG0P20/PPG00P21/PPG01P22/TO00P23/TO01P24/EC0P50/SCL0
I
P51/SDA0P52/PPG1AVRAVCC
H⎯⎯H HG
General-purpose I/O port
The pin is shared with UART/SIO ch.0 data input. General-purpose I/O port
The pin is shared with UART/SIO ch.0 data output. General-purpose I/O port
The pin is shared with UART/SIO ch.0 clock I/O.
General-purpose I/O port
The pin is shared with 16-bit PPG ch.0 trigger input (TRG0) and A/D converter trigger input (ADTG).General-purpose I/O port
The pin is shared with 16-bit PPG ch.0 output. General-purpose I/O port
The pins are shared with 8/16-bit PPG ch.0 output.General-purpose I/O port
The pins are shared with 8/16-bit compound timer ch.0 output.
General-purpose I/O port
The pin is shared with 8/16-bit compound timer ch.0 clock input.
General-purpose I/O port
The pin is shared with I2C ch.0 clock I/O. General-purpose I/O port
The pin is shared with I2C ch.0 data I/O. General-purpose I/O port
The pin is shared with 16-bit PPG ch.1 output. A/D converter reference input pinA/D converter power supply pin
(Continued)
C
General-purpose I/O port
The pins are shared with external interrupt input. Large current port.
I/Ocircuittype*3
⎯⎯
Function
Power supply pin (GND)Capacitor connection pin
10
MB95120MB Series
Pin no.
LQFP *1
2627282930313233343536373839404142
QFP *2
2930313233343536373839404142434445
Pin nameAVSSP30/AN00P31/AN01P32/AN02P33/AN03P34/AN04P35/AN05P36/AN06P37/AN07P40/AN08P41/AN09P42/AN10P43/AN11P53/TRG1P70/TO0
I/Ocircuittype*3
⎯
Function
A/D converter power supply pin (GND)
J
General-purpose I/O port
The pins are shared with A/D converter analog input.
J
General-purpose I/O port
The pins are shared with A/D converter analog input.General-purpose I/O port
The pin is shared with 16-bit PPG ch.1 trigger input. General-purpose I/O port
The pin is shared with 16-bit reload timer ch.0 output. General-purpose I/O port
The pin is shared with 16-bit reload timer ch.0 input. General-purpose I/O port
The pin is shared with LCDC SEG output (SEG39) and LIN-UART data input (SIN) .
General-purpose I/O port
The pin is shared with LCDC SEG output (SEG38) and LIN-UART data output (SOT) .
General-purpose I/O port
The pin is shared with LCDC SEG output (SEG37) and LIN-UART clock I/O (SCK) .
H
H
P71/TI0P67/SEG39/
SINP66/SEG38/
SOTP65/SEG37/
SCKP64/SEG36/
EC1P63/SEG35/
TO11P62/SEG34/
TO10
RSTX0AX1AVSS
B'A⎯MN
4346
4447
45464748495051
48495051525354
General-purpose I/O port
The pin is shared with LCDC SEG output (SEG36) and 8/16-bit compound timer ch.1 clock input (EC1) .
General-purpose I/O port
The pins are shared with LCDC SEG output (SEG34, SEG35) and 8/16-bit compound timer ch.1 output (TO10, TO11) .Reset pin
Sub clock oscillation pin (32 kHz) Power supply pin (GND)
(Continued)
11
MB95120MB Series
Pin no.
LQFP *1
52535455565758596061626364656667686970717273747576
QFP *2
55565758596061626364656667686970717273747576777879
Pin name
X1X0MODP61/SEG33/PPG11P60/SEG32/PPG10PE7/SEG31/INT13PE6/SEG30/INT12PE5/SEG29/INT11PE4/SEG28/INT10PE3/SEG27PE2/SEG26PE1/SEG25PE0/SEG24PD7/SEG23PD6/SEG22PD5/SEG21PD4/SEG20PD3/SEG19PD2/SEG18PD1/SEG17PD0/SEG16PC7/SEG15PC6/SEG14PC5/SEG13
VCC
I/Ocircuittype*3
AB
Function
Main clock oscillation pin
An operating mode designation pin
General-purpose I/O port
The pins are shared with LCDC SEG output (SEG32, SEG33) and 8/16-bit PPG ch.1 output (PPG10, PPG11) .
M
Q
General-purpose I/O port
The pins are shared with LCDC SEG output (SEG28 to SEG31) and external interrupt input (INT10 to INT13) .
M
General-purpose I/O port
The pins are shared with LCDC SEG output (SEG24 to SEG27) .
M
General-purpose I/O port
The pins are shared with LCDC SEG output (SEG16 to SEG23) .
M⎯
General-purpose I/O port
The pins are shared with LCDC SEG output (SEG13 to SEG15) . Power supply pin
(Continued)
12
MB95120MB Series
(Continued)
Pin no.LQFP *1
7778798081828384858687888990919293949596979899100
*1 : FPT-100P-M20*2 : FPT-100P-M06
*3 : For the I/O circuit type, refer to “■ I/O CIRCUIT TYPE”.
QFP *2
8081828384858687888990919293949596979899100123
Pin namePC4/SEG12PC3/SEG11PC2/SEG10PC1/SEG09PC0/SEG08PB7/SEG07PB6/SEG06PB5/SEG05PB4/SEG04PB3/SEG03PB2/SEG02PB1/SEG01PB0/SEG00PA3/COM3PA2/COM2PA1/COM1PA0/COM0
P95P94P93/V0P92/V1P91/V2P90/V3VCC
⎯
Power supply pinR
General-purpose I/O port
The pins are shared with power supply pins for LCDC drive. M
General-purpose I/O portM
General-purpose I/O port
The pins are shared with LCDC COM output (COM0 to COM3) . M
General-purpose I/O port
The pins are shared with LCDC SEG output (SEG00 to SEG07) . M
General-purpose I/O port
The pins are shared with LCDC SEG output (SEG08 to SEG12) .
I/Ocircuittype*3
Function
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MB95120MB Series
■I/O CIRCUIT TYPE
Type X1 (X1A) CircuitRemarks•Oscillation circuit•High-speed side Feedback resistance : approx. 1 MΩ•Low-speed sideFeedback resistance : approx. 10 MΩ Clock inputN-chA X0 (X0A) Standby controlBMode input•Only for input•Hysteresis input •Reset output•Hysteresis inputB’N-chReset inputReset outputP-chDigital outputDigital output•CMOSoutput•Hysteresis input•Automotive inputN-chCStandby controlExternal interrupt enableHysteresis inputAutomotive inputR P-chP-chPull-up controlDigital outputDigital outputCMOS inputHysteresis inputAutomotive input •••••CMOSoutputCMOS inputHysteresis inputWith pull-up controlAutomotive inputGN-chStandby control(Continued)
14
MB95120MB Series
TypeCircuit••••RemarksCMOSoutputHysteresis input With pull-up controlAutomotive inputR P-chP-chPull-up controlDigital outputDigital outputHysteresis inputAutomotive inputHN-chStandby controlN-chDigital outputCMOS inputHysteresis inputAutomotive inputI•••• N-ch open drain outputCMOSinputHysteresis inputAutomotive input Standby controlR P-chP-chPull-up controlDigital outputDigital outputAnalog inputHysteresis input•••••CMOSoutputHysteresis inputAnalog inputWith pull-up controlAutomotive input JN-chA/D controlStandby controlAutomotive input••••CMOSoutputLCD outputHysteresis inputAutomotive inputP-chDigital outputDigital outputLCD outputHysteresis inputAutomotive inputN-chMLCD controlStandby control(Continued)15
MB95120MB Series
(Continued)TypeCircuit•••••RemarksCMOS outputLCD outputCMOS inputHysteresis inputAutomotive inputP-chDigital outputDigital outputLCD outputCMOS inputHysteresis inputAutomotive inputN-chNLCD controlStandby controlP-chDigital outputDigital outputLCD outputHysteresis inputAutomotive inputN-ch••••CMOS outputLCD outputHysteresis inputAutomotive inputQLCD controlStandby controlExternalinterrupt controlP-chDigital outputDigital outputLCD built-in divisionresistance I/ON-ch••••CMOS outputLCD power supplyHysteresis inputAutomotive inputRHysteresis inputLCD controlStandby controlAutomotive input16
MB95120MB Series
■HANDLING DEVICES
• Preventing Latch-up
Care must be taken to ensure that maximum voltage ratings are not exceeded when they are used.
Latch-up may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pinsother than medium- and high-withstand voltage pins or if higher than the rating voltage is applied between VCCpin and VSS pin.
When latch-up occurs, power supply current increases rapidly and might thermally damage elements.Also, take care to prevent the analog power supply voltage (AVCC , AVR) and analog input voltage from exceedingthe digital power supply voltage (VCC) when the analog system power supply is turned on or off.• Stable Supply Voltage
Supply voltage should be stabilized.
A sudden change in power-supply voltage may cause a malfunction even within the guaranteed operating rangeof the VCC power-supply voltage.
For stabilization, in principle, keep the variation in VCC ripple (p-p value) in a commercial frequency range
(50/60 Hz) not to exceed 10% of the standard VCC value and suppress the voltage variation so that the transientvariation rate does not exceed 0.1 V/ms during a momentary change such as when the power supply is switched.• Precautions for Use of External Clock
Even when an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-upfrom sub clock mode or stop mode.
PIN CONNECTION
• Treatment of Unused Pin
Leaving unused input pins unconnected can cause abnormal operation or latch-up, leaving to permanent damage.
Unused input pins should always be pulled up or down through resistance of at least 2 kΩ. Any unused input/output pins may be set to output mode and left open, or set to input mode and treated the same as unused inputpins. If there is unused output pin, make it open.• Treatment of Power Supply Pins on A/D Converter
Connect to be AVCC = VCC and AVSS = AVR = VSS even if the A/D converter is not in use.
Noise riding on the AVCC pin may cause accuracy degradation. So, connect approx. 0.1 µF ceramic capacitoras a bypass capacitor between AVCC and AVSS pins in the vicinity of this device. • Power Supply Pins
In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the deviceto avoid abnormal operations including latch-up. However, you must connect the pins to external power supplyand a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signalscaused by the rise in the ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance.It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 µF between VCC and VSS nearthis device.
17
MB95120MB Series
• Mode Pin (MOD)
Connect the MOD pin directly to VCC or VSS pins.
To prevent the device unintentionally entering test mode due to noise, lay out the printed circuit board so as tominimize the distance from the MOD pins to VCC or VSS pins and to provide a low-impedance connection.Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. A bypass capacitor of VCC pinmust have a capacitance value higher than CS. For connection of smoothing capacitor CS, refer to the diagrambelow.
•C pin connection diagramCCS• Analog Power Supply
Always set the same potential to AVCC and VCC pins. When VCC > AVCC, the current may flow through the AN00to AN11 pins.
18
MB95120MB Series
■PROGRAMMING FLASH MEMORY MICROCONTROLLERS USING PARALLEL PROGRAMMER
• Supported Parallel Programmers and Adapters
The following table lists supported parallel programmers and adapters.
PackageApplicable adapter model
FPT-100P-M20FPT-100P-M06
TEF110-95F128HSPFVTEF110-95F128HSPF
Parallel programmers
AF9708 (Ver 02.35G or more)
AF9709/B (Ver 02.35G or more)AF9723+AF9834 (Ver 02.08E or more)
Note : For information on applicable adapter models and parallel programmers, contact the following:
Flash Support Group, Inc. TEL: +81-53-428-8380• Sector Configuration
The individual sectors of Flash memory correspond to addresses used for CPU access and programming bythe parallel programmer as follows:
• MB95F128MB/F128NB/F128JB (60 Kbytes)
Flash memoryCPU addressProgrammer address*
SA1 (4 Kbytes)SA2 (4 Kbytes)SA3 (4 Kbytes)SA4 (16 Kbytes)SA5 (16 Kbytes)SA6 (4 Kbytes)SA7 (4 Kbytes)SA8 (4 Kbytes)SA9 (4 Kbytes)
1000H1FFFH
2000H2FFFH3000H3FFFH4000H7FFFH8000HBFFFHC000HCFFFHD000HDFFFHE000HEFFFHF000HFFFFH
71000H
Lower bankUpper bank71FFFH72000H72FFFH73000H73FFFH74000H77FFFH78000H7BFFFH7C000H7CFFFH7D000H7DFFFH7E000H7EFFFH7F000H7FFFFH
*:Programmer addresses are corresponding to CPU addresses, used when the parallel programmer programs data into Flash memory.
These programmer addresses are used for the parallel programmer to program or erase data in Flash memory.• Programming Method
1) Set the type code of the parallel programmer to 17222.
2) Load program data to programmer addresses 71000H to 7FFFFH.3) Programmed by parallel programmer
19
MB95120MB Series
• MB95F126MB/F126NB/F126JB (32 Kbytes)
Flash memoryCPU addressProgrammer address*SA5 (16 Kbytes)SA6 (4 Kbytes)SA7 (4 Kbytes)SA8 (4 Kbytes)SA9 (4 Kbytes)
8000HBFFFH
C000HCFFFHD000HDFFFHE000HEFFFHF000HFFFFH
78000H7BFFFH7C000H7CFFFH7D000H7DFFFH7E000H7EFFFH7F000H7FFFFH
*:Programmer addresses are corresponding to CPU addresses, used when the parallel programmer programs data into Flash memory.
These programmer addresses are used for the parallel programmer to program or erase data in Flash memory.• Programming Method
1) Set the type code of the parallel programmer to 17222.
2) Load program data to programmer addresses 78000H to 7FFFFH.3) Programmed by parallel programmer
• MB95F124MB/F124NB/F124JB (16 Kbytes)
Flash memoryCPU addressProgrammer address*
SA6 (4 Kbytes)SA7 (4 Kbytes)SA8 (4 Kbytes)SA9 (4 Kbytes)
C000HCFFFH
D000HDFFFHE000HEFFFHF000HFFFFH
7C000H7CFFFH7D000H7DFFFH7E000H7EFFFH7F000H7FFFFH
*:Programmer addresses are corresponding to CPU addresses, used when the parallel programmer programs data into Flash memory.
These programmer addresses are used for the parallel programmer to program or erase data in Flash memory.• Programming Method
1) Set the type code of the parallel programmer to 17222.
2) Load program data to programmer addresses 7C000H to 7FFFFH.3) Programmed by parallel programmer20
MB95120MB Series
■BLOCK DIAGRAM FMC-8FX CPURSTX0/X1X0A/X1AReset controlClock controlWatch prescalerWatch counterP00/INT00 to P07/INT07 P10/UI0P11/UO0P12/UCK0P13/TRG0/ADTGP14/PPG0P20/PPG00P21/PPG01P22/TO00P23/TO01P24/EC0P30/AN00 to P37/AN07P40/AN08 to P43/AN11AVCCAVSSAVR P50/SCL0P51/SDA0P52/PPG1P53/TRG1I2C1 channel16-bit PPG ch.11 channelPortOther pinsMOD, VCC,Vss,CExternal interrupt ch.8 to ch.114 channelsExternal interrupt ch.0 to ch.78 channels2ROM (60 Kbytes)RAM (2 Kbytes)Interrupt controlWild registerP60/SEG32/PPG10P61/SEG33/PPG11P62/SEG34/TO10P63/SEG35/TO11P64/SEG36/EC1P65/SEG37/SCKP66/SEG38/SOTP67/SEG39/SINP70/TO0P71/TI0P90/V3 to P93/V0P94/P95PA0/COM0 to PA3/COM3PB0/SEG00 to PB7/SEG07PC0/SEG08 to PC7/SEG15PD0/SEG16 to PD7/SEG23PE0/SEG24 to PE3/SEG27PE4/SEG28/INT10PE5/SEG29/INT11PE6/SEG30/INT12PE7/SEG31/INT138/16-bit PPG ch.11 channel8/16-bitcompound timer ch.11 channelInternal busLIN-UART1 channel16-bit reload timer1 channelUART/SIO1 channel16-bit PPG ch.0 1 channel8/16-bit PPG ch.0 1 channel8/16-bit compoundtimer ch.01 channel8/10-bit A/D converter12 channelsLCDCPort21
MB95120MB Series
■CPU CORE
1.Memory space
Memory space of the MB95120MB series is 64 Kbytes and consists of I/O area, data area, and program area.The memory space includes special - purpose areas such as the general - purpose registers and vector table.Memory map of the MB95120MB series is shown below. •Memory MapMB95F124MB/F124NB/F124JBMB95F126MB/F126NB/F126JBMB95F128MB/F128NB/F128JB0000H0080H0100H0200HAccess prohibitedExtended I/O1000HAddress #2Address #10F80HExtended I/O1000HAccess prohibited0F80HExtended I/OI/ORAMRegisterMB95128MB0000H0080H0100H0200H0880H0F80HI/ORAM 2 KbytesRegisterMB95FV100D-1030000H0080H0100H0200HI/ORAM 3.75 KbytesRegisterMASK ROM60 KbytesFlash memoryFlash memory60 KbytesFFFFHFFFFHFFFFHFlash memory
MB95F124MBMB95F124NBMB95F124JBMB95F126MBMB95F126NBMB95F126JBMB95F128MBMB95F128NBMB95F128JB
60 Kbytes32 Kbytes16 Kbytes
RAM512 bytes
Address #10280H
Address #2C000H
1 Kbyte0480H8000H
2 Kbytes0880H1000H
22
MB95120MB Series
2.Register
The MB95120MB series has two types of registers; dedicated registers in the CPU and general-purpose registersin the memory. The dedicated registers are as follows:Program counter (PC) : A 16-bit register to indicate locations where instructions are stored.Accumulator (A) : A 16-bit register for temporary storage of arithmetic operations. In the case of
an 8-bit data processing instruction, the lower 1 byte is used.
Temporary accumulator (T) : A 16-bit register which performs arithmetic operations with the accumulator.
In the case of an 8-bit data processing instruction, the lower 1 byte is used.
Index register (IX) : A 16-bit register for index modificationExtra pointer (EP) : A 16-bit pointer to point to a memory address.Stack pointer (SP) : A 16-bit register to indicate a stack area.Program status (PS) : A 16-bit register for storing a register bank pointer, a direct bank pointer, and
a condition code register
16-bitPCAHTHIXEPSPPSALTLInitial Value : Program counter : Accumulator : Temporary accumulator : Index register : Extra pointer : Stack pointer : Program statusFFFDH0000H0000H0000H0000H0000H0030HThe PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and a direct bank pointer(DP) and the lower 8 bits for use as a condition code register (CCR) . (Refer to the diagram below.)• Structure of the program statusbit 15bit 14bit 13bit 12bit 11bit 10bit 9PSR4R3R2R1R0DP2DP1bit 8DP0bit 7Hbit 6Ibit 5IL1bit 4IL0bit 3Nbit 2Zbit 1Vbit 0CRPDPCCR23
MB95120MB Series
The RP indicates the address of the register bank currently being used. The relationship between the contentof RP and the real address conforms to the conversion rule illustrated below: • Rule for Conversion of Actual Addresses in the General-purpose Register AreaRP upper\"0\"\"0\"\"0\"\"0\"\"0\"\"0\"\"0\"A9\"1\"A8R4A7R3A6R2A5R1A4OP code lowerR0A3b2A2b1A1b0A0Generated addressA15A14A13A12A11A10The DP specifies the area for mapping instructions (16 different instructions such as MOV A, dir) using directaddresses to 0080H to 00FFH.
Direct bank pointer (DP2 to DP0)Specified address areaMapping area
XXXB (no effect to mapping)
000B (initial value)
001B010B011B100B101B110B111B
0080H to 00FFH0000H to 007FH
0000H to 007FH (without mapping) 0080H to 00FFH (without mapping)
0100H to 017FH0180H to 01FFH0200H to 027FH0280H to 02FFH0300H to 037FH0380H to 03FFH0400H to 047FH
The CCR consists of the bits indicating arithmetic operation results or transfer data contents and the bits thatcontrol CPU operations at interrupt.H flag
: Set to “1” when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared to “0” otherwise. This flag is for decimal adjustment instructions.
I flag : Interrupt is enabled when this flag is set to “1”. Interrupt is disabled when this flag is set to “0”.
The flag is cleared to “0” when reset.
IL1, IL0 : Indicates the level of the interrupt currently enabled. Processes an interrupt only if its request level
is higher than the value indicated by these bits.
IL10011N flagZ flagV flagC flag
IL00101
Interrupt level
0123
Low (no interruption) PriorityHigh
: Set to “1” if the MSB is set to “1” as the result of an arithmetic operation. Cleared to “0” when the
bit is set to “0”.
: Set to “1” when an arithmetic operation results in “0”. Cleared to “0” otherwise.
: Set to “1” if the complement on 2 overflows as a result of an arithmetic operation. Cleared to “0” otherwise.
: Set to “1” when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to “0” otherwise. Set to the shift-out value in the case of a shift instruction.
24
MB95120MB Series
The following general-purpose registers are provided:
General-purpose registers: 8-bit data storage registers
The general-purpose registers are 8 bits and located in the register banks on the memory. 1-bank contains 8registers. Up to a total of 32 banks can be used on the MB95120MB series. The bank currently in use is indicatedby the register bank pointer (RP).8-register. Up to a total of 32 banks can be used on the MB95120MB series.The bank currently in use is specified by the register bank pointer (RP), and the lower 3 bits of OP code indicatesthe general-purpose register 0 (R0) to general-purpose register 7 (R7).•Register Bank Configuration8-bit1F8HThis address = 0100H + 8 × (RP)Address 100HR0R1R2R3R4R5107HR6R7Bank 0R0R0R1R2R3R4R5R6R7R1R2R3R4R5R6R7Bank 311FFH32 banks32 banks (RAM area) The number of banks is limited by the usable RAM capacitance.Memory area25
MB95120MB Series
■I/O MAPAddress0000H0001H0002H0003H0004H0005H0006H0007H0008H0009H000AH000BH000CH000DH000EH000FH0010H0011H0012H0013H0014H0015H0016H0017H0018H0019H001AH, 001BH001CH001DH001EH001FH0020H0021H0022H
Register abbreviation
PDR0DDR0PDR1DDR1⎯WATRPLLCSYCCSTBCRSRRTBTCWPCRWDTC⎯PDR2DDR2PDR3DDR3PDR4DDR4PDR5DDR5PDR6DDR6PDR7DDR7⎯PDR9DDR9PDRADDRAPDRBDDRBPDRC
Register namePort 0 data registerPort 0 direction registerPort 1 data registerPort 1 direction register
(Disabled)
Oscillation stabilization wait time setting register
PLL control register System clock control register Standby control register Reset source registerTimebase timer control register Watch prescaler control register Watchdog timer control register
(Disabled) Port 2 data registerPort 2 direction registerPort 3 data registerPort 3 direction registerPort 4 data registerPort 4 direction registerPort 5 data registerPort 5 direction registerPort 6 data registerPort 6 direction registerPort 7 data registerPort 7 direction register
(Disabled) Port 9 data registerPort 9 direction registerPort A data registerPort A direction registerPort B data registerPort B direction registerPort C data register
R/WR/WR/WR/WR/W⎯R/WR/WR/WR/WR/WR/WR/WR/W⎯R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W⎯R/WR/WR/WR/WR/WR/WR/W
Initial value00000000B00000000B00000000B00000000B
⎯11111111B00000000B1010X011B00000000BXXXXXXXXB00000000B00000000B00000000B
⎯00000000B00000000B00000000B00000000B00000000B00000000B00000000B00000000B00000000B00000000B00000000B00000000B
⎯00000000B00000000B00000000B00000000B00000000B00000000B00000000B(Continued)
26
MB95120MB Series
Address0023H0024H0025H0026H0027H0028H to 002CH002DH002EH002FH0030H0031H0032H0033H to 0035H0036H0037H0038H0039H003AH003BH003CH003DH003EH003FH0040H, 0041H0042H0043H0044H0045H0046H, 0047H0048H0049H
Register abbreviation
DDRCPDRDDDRDPDREDDRE⎯PUL1PUL2PUL3PUL4PUL5PUL7⎯T01CR1T00CR1T11CR1T10CR1PC01PC00PC11PC10TMCSRH0TMCSRL0
⎯PCNTH0PCNTL0PCNTH1PCNTL1⎯EIC00EIC10
Register namePort C direction registerPort D data registerPort D direction registerPort E data registerPort E direction register
(Disabled) Port 1 pull-up registerPort 2 pull-up registerPort 3 pull-up registerPort 4 pull-up registerPort 5 pull-up registerPort 7 pull-up register
(Disabled)
8/16-bit compound timer 01 control status register 1 ch.08/16-bit compound timer 00 control status register 1 ch.08/16-bit compound timer 11 control status register 1 ch.18/16-bit compound timer 10 control status register 1 ch.1
8/16-bit PPG1 control register ch.08/16-bit PPG0 control register ch.08/16-bit PPG1 control register ch.18/16-bit PPG0 control register ch.1
16-bit reload timer control status register (upper byte) ch.016-bit reload timer control status register (lower byte) ch.0
(Disabled)
16-bit PPG status control register (upper byte) ch.016-bit PPG status control register (lower byte) ch.016-bit PPG status control register (upper byte) ch.116-bit PPG status control register (lower byte) ch.1
(Disabled)
External interrupt circuit control register ch.0/ch.1External interrupt circuit control register ch.2/ch.3
R/WR/WR/WR/WR/WR/W⎯R/WR/WR/WR/WR/WR/W⎯R/WR/WR/WR/WR/WR/WR/WR/WR/WR/W⎯R/WR/WR/WR/W⎯R/WR/W
Initial value00000000B00000000B00000000B00000000B00000000B
⎯00000000B00000000B00000000B00000000B00000000B00000000B
⎯00000000B00000000B00000000B00000000B00000000B00000000B00000000B00000000B00000000B00000000B
⎯00000000B00000000B00000000B00000000B
⎯00000000B00000000B(Continued)
27
MB95120MB Series
Address004AH004BH004CH004DH004EH, 004FH0050H0051H0052H0053H0054H0055H0056H0057H0058H0059H005AH005BH to 005FH0060H0061H0062H0063H0064H0065H0066H to 006BH006CH006DH006EH006FH0070H0071H0072H
Register abbreviation
EIC20EIC30EIC01EIC11⎯SCRSMRSSRRDR/TDRESCRECCRSMC10SMC20SSR0TDR0RDR0⎯IBCR00IBCR10IBSR0IDDR0IAAR0ICCR0⎯ADC1ADC2ADDHADDLWCSR⎯FSR
Register name
External interrupt circuit control register ch.4/ch.5External interrupt circuit control register ch.6/ch.7External interrupt circuit control register ch.8/ch.9External interrupt circuit control register ch.10/ch.11
(Disabled)
LIN-UART serial control register LIN-UART serial mode registerLIN-UART serial status register
LIN-UART reception/transmission data registerLIN-UART extended status control register LIN-UART extended communication control registerUART/SIO serial mode control register 1 ch.0UART/SIO serial mode control register 2 ch.0
UART/SIO serial status register ch.0UART/SIO serial output data register ch.0UART/SIO serial input data register ch.0
(Disabled)
I2C bus control register 0 ch.0I2C bus control register 1 ch.0I2C bus status register ch.0I2C data register ch.0I2C address register ch.0I2C clock control register ch.0
(Disabled)
8/10-bit A/D converter control register 18/10-bit A/D converter control register 28/10-bit A/D converter data register (upper byte) 8/10-bit A/D converter data register (lower byte)
Watch counter status register
(Disabled)
Flash memory status register
R/WR/WR/WR/WR/W⎯R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR⎯R/WR/WRR/WR/WR/W⎯R/WR/WR/WR/WR/W⎯R/W
Initial value00000000B00000000B00000000B00000000B
⎯00000000B00000000B00001000B00000000B00000100B000000XXB00000000B00100000B00000001B00000000B00000000B
⎯00000000B00000000B00000000B00000000B00000000B00000000B
⎯00000000B00000000B00000000B00000000B00000000B
⎯000X0000B(Continued)
28
MB95120MB Series
Address0073H0074H0075H0076H0077H0078H0079H007AH007BH007CH007DH007EH007FH0F80H0F81H0F82H0F83H0F84H0F85H0F86H0F87H0F88H0F89H to 0F91H0F92H0F93H0F94H0F95H0F96H0F97H0F98H0F99H0F9AH
Register abbreviationSWRE0SWRE1⎯WRENWROR⎯ILR0ILR1ILR2ILR3ILR4ILR5⎯WRARH0WRARL0WRDR0WRARH1WRARL1WRDR1WRARH2WRARL2WRDR2⎯T01CR0T00CR0T01DRT00DRTMCR0T11CR0T10CR0T11DRT10DR
Register name
Flash memory sector writing control register 0Flash memory sector writing control register 1
(Disabled)
Wild register address compare enable register
Wild register data test setting registerRegister bank pointer (RP) , Mirror of direct bank pointer (DP) Interrupt level setting register 0Interrupt level setting register 1Interrupt level setting register 2Interrupt level setting register 3Interrupt level setting register 4Interrupt level setting register 5
(Disabled)
Wild register address setting register (upper byte) ch.0Wild register address setting register (lower byte) ch.0
Wild register data setting register ch.0
Wild register address setting register (upper byte) ch.1Wild register address setting register (lower byte) ch.1
Wild register data setting register ch.1
Wild register address setting register (upper byte) ch.2Wild register address setting register (lower byte) ch.2
Wild register data setting register ch.2
(Disabled)
8/16-bit compound timer 01 control status register 0 ch.08/16-bit compound timer 00 control status register 0 ch.0
8/16-bit compound timer 01 data register ch.08/16-bit compound timer 00 data register ch.08/16-bit compound timer 00/01 timer mode control register
ch.08/16-bit compound timer 11 control status register 0 ch.18/16-bit compound timer 10 control status register 0 ch.1
8/16-bit compound timer 11 data register ch.18/16-bit compound timer 10 data register ch.1
R/WR/WR/W⎯R/WR/W⎯R/WR/WR/WR/WR/WR/W⎯R/WR/WR/WR/WR/WR/WR/WR/WR/W⎯R/WR/WR/WR/WR/WR/WR/WR/WR/W
Initial value00000000B00000000B
⎯00000000B00000000B
⎯11111111B11111111B11111111B11111111B11111111B11111111B
⎯00000000B00000000B00000000B00000000B00000000B00000000B00000000B00000000B00000000B
⎯00000000B00000000B00000000B00000000B00000000B00000000B00000000B00000000B00000000B(Continued)
29
MB95120MB Series
Address0F9BH0F9CH0F9DH0F9EH0F9FH0FA0H0FA1H0FA2H0FA3H0FA4H0FA5H0FA6H0FA7H0FA8H, 0FA9H0FAAH0FABH0FACH0FADH0FAEH0FAFH0FB0H0FB1H0FB2H0FB3H0FB4H0FB5H0FB6H to 0FBBH0FBCH0FBDH0FBEH
Register abbreviationTMCR1PPS01PPS00PDS01PDS00PPS11PPS10PDS11PDS10PPGSREVCTMRH0/TMRLRH0TMRL0/TMRLRL0
⎯PDCRH0PDCRL0PCSRH0PCSRL0PDUTH0PDUTL0PDCRH1PDCRL1PCSRH1PCSRL1PDUTH1PDUTL1⎯BGR1BGR0PSSR0
Register name
8/16-bit compound timer 10/11 timer mode control register
ch.1
8/16-bit PPG1 cycle setting buffer register ch.08/16-bit PPG0 cycle setting buffer register ch.08/16-bit PPG1 duty setting buffer register ch.08/16-bit PPG0 duty setting buffer register ch.08/16-bit PPG1 cycle setting buffer register ch.18/16-bit PPG0 cycle setting buffer register ch.18/16-bit PPG1 duty setting buffer register ch.18/16-bit PPG0 duty setting buffer register ch.1
8/16-bit PPG start register8/16-bit PPG output inversion register
16-bit reload timer timer/reload register (upper byte) ch.016-bit reload timer timer/reload register (lower byte) ch.0
(Disabled)
16-bit PPG down counter register (upper byte) ch.016-bit PPG down counter register (lower byte) ch.016-bit PPG cycle setting buffer register (upper byte) ch.016-bit PPG cycle setting buffer register (lower byte) ch.016-bit PPG duty setting buffer register (upper byte) ch.016-bit PPG duty setting buffer register (lower byte) ch.016-bit PPG down counter register (upper byte) ch.116-bit PPG down counter register (lower byte) ch.116-bit PPG cycle setting buffer register (upper byte) ch.116-bit PPG cycle setting buffer register (lower byte) ch.116-bit PPG duty setting buffer register (upper byte) ch.116-bit PPG duty setting buffer register (lower byte) ch.1
(Disabled)
LIN-UART baud rate generator register 1LIN-UART baud rate generator register 0UART/SIO dedicated baud rate generator
prescaler select register ch.0
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W⎯RRR/WR/WR/WR/WRRR/WR/WR/WR/W⎯R/WR/WR/W
Initial value00000000B11111111B11111111B11111111B11111111B11111111B11111111B11111111B11111111B00000000B00000000B00000000B00000000B
⎯00000000B00000000B11111111B11111111B11111111B11111111B00000000B00000000B11111111B11111111B11111111B11111111B
⎯00000000B00000000B00000000B(Continued)
30
MB95120MB Series
Address0FBFH0FC0H, 0FC1H0FC2H0FC3H0FC4H0FC5H0FC6H0FC7H0FC8H0FC9H0FCAH0FCBH0FCCH0FCDH
to 0FE0H0FE1H, 0FE2H0FE3H0FE4H, 0FE5H0FE6H0FE7H0FE8H, 0FE9H0FEAH0FEBH
to 0FEDH0FEEH0FEFH0FF0H to 0FFFH
Register abbreviationBRSR0⎯AIDRHAIDRLLCDCCLCDCE1LCDCE2LCDCE3LCDCE4LCDCE5LCDCE6LCDCB1LCDCB2LCDRAM
⎯WCDR⎯ILSR3ILSR2⎯CSVCR⎯ILSRWICR⎯
Register name
UART/SIO dedicated baud rate generator
baud rate setting register ch.0
(Disabled)
A/D input disable register (upper byte) A/D input disable register (lower byte)
LCDC control register LCDC enable register 1LCDC enable register 2LCDC enable register 3LCDC enable register 4LCDC enable register 5LCDC enable register 6LCDC blinking setting register 1LCDC blinking setting register 2
LCDC display RAM
(Disabled)
Watch counter data register
(Disabled)
Input level select register 3Input level select register 2
(Disabled)
Clock supervisor control register
(Disabled)
Input level select register
Interrupt pin select circuit control register
(Disabled)
R/WR/W⎯R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W⎯R/W⎯R/WR/W⎯R/W⎯R/WR/W⎯
Initial value00000000B
⎯00000000B00000000B00010000B00110000B00000000B00000000B00000000B00000000B00000000B00000000B00000000B00000000B
⎯00111111B
⎯00000000B00000000B
⎯00011100B
⎯00000000B01000000B
⎯(Continued)
31
MB95120MB Series
(Continued)
• R/W access symbols
R/W : Readable/WritableR : Read onlyW : Write only• Initial value symbols
0 : The initial value of this bit is “0”.1 : The initial value of this bit is “1”.X : The initial value of this bit is undefined.
Note : Do not write to the “ (Disabled) ”. Reading the “ (Disabled) ” returns an undefined value.
32
MB95120MB Series
■INTERRUPT SOURCE TABLE
Interrupt source
External interrupt ch.0External interrupt ch.4External interrupt ch.1External interrupt ch.5External interrupt ch.2External interrupt ch.6External interrupt ch.3External interrupt ch.7UART/SIO ch.0
8/16-bit compound timer ch.0 (Lower)8/16-bit compound timer ch.0 (Upper)LIN-UART (reception) LIN-UART (transmission) 8/16-bit PPG ch.1 (Lower)8/16-bit PPG ch.1 (Upper)16-bit reload timer ch.08/16-bit PPG ch.0 (Upper)8/16-bit PPG ch.0 (Lower)
8/16-bit compound timer ch.1 (Upper)16-bit PPG ch.0I2C ch.016-bit PPG ch.18/10-bit A/D converterTimebase timer
Watch prescaler/watch counterExternal interrupt ch.8External interrupt ch.9External interrupt ch.10External interrupt ch.11
8/16-bit compound timer ch.1 (Lower)Flash memory
IRQ22IRQ23
FFCEHFFCCH
FFCFHFFCDH
L22 [1 : 0]L23 [1 : 0]
Low
IRQ21
FFD0H
FFD1H
L21 [1 : 0]
Interrupt request numberIRQ0IRQ1IRQ2IRQ3IRQ4IRQ5IRQ6IRQ7IRQ8IRQ9IRQ10IRQ11IRQ12IRQ13IRQ14IRQ15IRQ16IRQ17IRQ18IRQ19IRQ20
Vector table addressUpperFFFAHFFF8HFFF6HFFF4HFFF2HFFF0HFFEEHFFECHFFEAHFFE8HFFE6HFFE4HFFE2HFFE0HFFDEHFFDCHFFDAHFFD8HFFD6HFFD4HFFD2H
LowerFFFBHFFF9HFFF7HFFF5HFFF3HFFF1HFFEFHFFEDHFFEBHFFE9HFFE7HFFE5HFFE3HFFE1HFFDFHFFDDHFFDBHFFD9HFFD7HFFD5HFFD3H
Same level
Bit name of
priority order
interrupt level
(at simultaneous
setting register
occurrence)L00 [1 : 0]L01 [1 : 0]L02 [1 : 0]L03 [1 : 0]L04 [1 : 0]L05 [1 : 0]L06 [1 : 0]L07 [1 : 0]L08 [1 : 0]L09 [1 : 0]L10 [1 : 0]L11 [1 : 0]L12 [1 : 0]L13 [1 : 0]L14 [1 : 0]L15 [1 : 0]L16 [1 : 0]L17 [1 : 0]L18 [1 : 0]L19 [1 : 0]L20 [1 : 0]
High
33
MB95120MB Series
■ELECTRICAL CHARACTERISTICS
1.Absolute Maximum Ratings
Parameter
SymbolVccAVccAVR
Power supply voltage for LCD
Input voltage*1Output voltage*1
Maximum clamp currentTotal maximum clamp current
“L” level maximum output current
V0 to V3
VIVOICLAMPΣ|ICLAMP|IOL1IOL2IOLAV1
“L” level average current
IOLAV2
“L” level total maximum output current“L” level total average output current“H” level maximum output current
⎯
12
RatingMinVss − 0.3Vss − 0.3VSS − 0.3Vss − 0.3Vss − 0.3 − 2.0⎯⎯
MaxVss + 6.0Vss + 6.0VSS + 6.0Vss + 6.0Vss + 6.0 + 2.02015154
mAVVVmAmAmAUnit
*2*2*3*4*4
Applicable to pins*5Applicable to pins*5Other than P00 to P07P00 to P07
Other than P00 to P07Average output current =
operating current × operating ratio(1 pin)
P00 to P07
Average output current =
operating current × operating ratio(1 pin)
Remarks
Power supply voltage*1V
ΣIOLΣIOLAVIOH1IOH2IOHAV1
⎯⎯⎯
10050 − 15 − 15 − 4
mAmA
Total average output current = operating current × operating ratio(Total of pins) Other than P00 to P07P00 to P07
Other than P00 to P07Average output current =
operating current × operating ratio(1 pin)
P00 to P07
Average output current =
operating current × operating ratio(1 pin)
mA
“H” level average current
IOHAV2
“H” level total maximum output current“H” level total average output current
⎯
− 8
mA
ΣIOHΣIOHAV
⎯⎯
− 100 − 50
mAmA
Total average output current = operating current × operating ratio(Total of pins)
(Continued)
34
MB95120MB Series
(Continued)
ParameterPower consumptionOperating temperatureStorage temperature
SymbolPdTATstg
RatingMin⎯ − 40 − 55
Max320 + 105 + 150
UnitmW °C °C
Remarks
*1 : The parameter is based on AVSS = VSS = 0.0 V.
*2 : Apply equal potential to AVcc and Vcc. AVR should not exceed AVcc + 0.3 V. *3 : V0 to V3 should not exceed VCC + 0.3 V.
*4 : VI and Vo should not exceed VCC + 0.3 V. VI must not exceed the rating voltage. However, if the maximum current
to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI rating.*5 : Applicable to pins : P00 to P07, P10 to P14, P20 to P24, P30 to P37, P40 to P43, P52, P53
• Use within recommended operating conditions.• Use at DC voltage (current).
• +B signal is an input signal that exceeds VCC voltage. The + B signal should always be applied a limiting resistance placed between the + B signal and the microcontroller.
• The value of the limiting resistance should be set so that when the + B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. • Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this affects other devices.
• Note that if the + B signal is inputted when the microcontroller power supply is off (not fixed at 0 V), the power supply is provided from the pins, so that incomplete operation may result.
• Note that if the + B input is applied during power-on, the power supply is provided from the pins and the resulting power supply voltage may not be sufficient to operate the power-on reset.• Care must be taken not to leave the + B input pin open.
•Note that analog system input/output pins other than the A/D input pins (LCD drive pins, etc.) cannot accept +B signal input.
• Sample recommended circuits : • Input/Output Equivalent circuitsProtective diodeLimitingresistance + B input (0 V to 16 V)RVccP-chN-chWARNING:Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
35
MB95120MB Series
2.Recommended Operating Conditions
(AVSS = VSS = 0.0 V)
Parameter
Symbol
Condi-tion
ValueMin2.42*1,*2
Power supply voltage
VCC, AVCC
2.32.72.3
Power supply voltage for LCDA/D converter reference input voltageSmoothing capacitorOperating temperature
V0 to V3
Max5.5*15.55.55.5
VVUnit
Remarks
In normal operatingHold condition in STOP modeIn normal operatingHold condition in STOP mode
MB95FV100D-103Other than
MB95FV100D-103
⎯
VSS VCC
The range of liquid crystal power supply (The optimal value depends on liquid crystal display elements used.)
AVRCSTA
4.00.1 − 40 +5
AVCC1.0 + 105+ 35
VµF °C °C
*3
Other than MB95FV100D-103MB95FV100D-103
*1 : The values vary with the operating frequency, machine clock or analog guarantee range.*2 : The value is 2.88 V when the low voltage detection reset is used.
*3 : Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. A bypass capacitor of VCC
pin must have a capacitor value higher than CS. For connection of smoothing capacitor CS, refer to the diagram below. •C pin connection diagramCCSWARNING:The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device isoperated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operationoutside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented onthe data sheet. Users considering application outside the listed conditions are advised to contact theirFUJITSU representatives beforehand.
36
MB95120MB Series
3.DC Characteristics
(VCC = AVCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
ValueCondi-UnitRemarksParameterSymbolPin name
tionMinTypMaxHysteresis inputP10 (selectable at UI0) ,
VIH1⎯0.7 VCC⎯VCC + 0.3V (When selecting
P67 (selectable at SIN)
CMOS input level)
P50, P51VIH2⎯VSS + 5.5V⎯0.7 VCC
(selectable at I2C)
P00 to P07, P10 to P14, P20 to P24, P30 to P37, P40 to P43, P50 to P53, P60 to P67, P70, P71,
Port inputs if Auto-P90 to P95,
VIHA⎯0.8 VCC⎯VCC + 0.3Vmotive input levels
PA0 to PA3,
are selected
PB0 to PB7, PC0 to PC7, PD0 to PD7, PE0 to PE7
P00 to P07, P10 to P14, “H” level input
P20 to P24, P30 to P37,
voltage
P40 to P43, P50 to P53, P60 to P67, P70, P71, P90 to P95,
VIHS1⎯0.8 VCC⎯VCC + 0.3VHysteresis input
PA0 to PA3, PB0 to PB7, PC0 to PC7, PD0 to PD7, PE0 to PE7
VIHS2P50, P51⎯0.8 VCC⎯VSS + 5.5VCMOS input⎯0.7 VCC⎯VCC + 0.3V (Flash memory
product)
RST, MODVIHMHysteresis input (MASK ROM
⎯0.8 VCC⎯VCC + 0.3V
product)
P10 (selectable at UI0) , P50, P51
(selectable at I2C)
P67 (selectable at SIN) P00 to P07, P10 to P14, P20 to P24, P30 to P37, P40 to P43, P50 to P53, P60 to P67, P70, P71, P90 to P95, PA0 to PA3, PB0 to PB7, PC0 to PC7, PD0 to PD7, PE0 to PE7
Hysteresis input (When selecting CMOS input level)
VIL
⎯VSS − 0.3⎯0.3 VCCV
“L” level input voltage
VILA
⎯VSS − 0.3⎯0.5 VCCV
Port inputs if Automotive input levels are selected
(Continued)
37
MB95120MB Series
(VCC = AVCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
Parameter
Symbol
Pin nameP00 to P07P10 to P14, P20 to P24, P30 to P37, P40 to P43, P50 to P53, P60 to P67, P70, P71, P90 to P95, PA0 to PA3, PB0 to PB7, PC0 to PC7, PD0 to PD7, PE0 to PE7
Condition
Value
Min
Typ
Unit
Max
Remarks
VILS
⎯VSS − 0.3⎯0.2 VCCVHysteresis input
“L” level input
voltage
⎯
VILM
RST, MOD⎯
Open-drain output application voltage“H” level output voltage
VSS − 0.3⎯0.3 VCCV
CMOS input (Flash memory product) Hysteresis input (MASK ROM product)
VSS − 0.3⎯0.2 VCCV
VD1P50, P51⎯VSS − 0.3⎯VSS + 5.5V
VOH1VOH2VOL1VOL2
Output pin other
IOH = − 4.0 mAVcc − 0.5
than P00 to P07P00 to P07
IOH = − 8.0 mAVcc − 0.5
⎯⎯ − 5
Output pin other than P00 to IOL = 4.0 mAP07, RST*1P00 to P07
IOL = 12 mA
⎯⎯⎯⎯⎯
⎯⎯0.40.4 +5
VVVVµA
When the pull-up prohibition setting
“L” level output voltageInput leakage current (Hi-Z output leakage current)Open-drain output leakage current
ILI
Port other than 0.0 V < VI < P50, P51VCC
0.0 V < VI <
VSS + 5.5 V
ILIODP50, P51
⎯⎯5µA
(Continued)
38
MB95120MB Series
(VCC = AVCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
Parameter
Sym-bol
Pin nameP10 to P14, P20 to P24, P30 to P37, P40 to P43, P52, P53, P70, P71
Condition
Value
Min
Typ
Max
Unit
Remarks
Pull-up resistor
RPULLVI = 0.0 V2550100kΩ
When the pull-up
permission set-ting
MASK ROM product only
Pull-down resistorInput
capacitance
RMODMODCIN
VI = VCC50⎯
1005
20015
kΩpF
Other than AVCC,
AVSS, AVR, VCC, f = 1 MHzVSS
⎯
FCH = 20 MHzFMP = 10 MHzMain clock mode (divided by 2)
9.512.5
Flash memory product
(at other than mA
Flash memory writing and erasing) Flash memory productmA (at Flash
memory writing and erasing) mA
MASK ROM product
⎯30.035.0
Power supply current*2
ICC
VCC
(External clock operation)
⎯7.29.5
⎯
FCH = 32 MHzFMP = 16 MHzMain clock mode (divided by 2)
15.220.0
Flash memory product
(at other than mA
Flash memory writing and erasing) Flash memory productmA (at Flash
memory writing and erasing) mA
MASK ROM product
(Continued)
⎯35.742.5
⎯11.615.2
39
MB95120MB Series
(VCC = AVCC = 5.0 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
Parameter
Sym-bol
Pin name
ConditionFCH = 20 MHzFMP = 10 MHzMain Sleep mode (divided by 2) FCH = 32 MHzFMP = 16 MHzMain Sleep mode (divided by 2) FCL = 32 kHzFMPL = 16 kHzSub clock mode (divided by 2) FCL = 32 kHzFMPL = 16 kHzSub sleep mode (divided by 2) FCL = 32 kHzWatch modeMain stop modeTA = + 25 °CFCH = 4 MHzFMP = 10 MHzMain PLL mode (multiplied by 2.5)
ICCMPLL
FCH = 6.4 MHzFMP = 16 MHzMain PLL mode (multiplied by 2.5)
⎯
14.9
20.0
Value
Min⎯
Typ4.5
Max7.5
UnitRemarks
mA
ICCS
⎯7.212.0mA
ICCL
⎯45100µA
ICCLS
Power supply current*2
ICCT
VCC
(External clock operation)
⎯1081µA
⎯4.627.0 µA
Flash mAmemory
productMASK mAROM
productFlash mAmemory
productMASK mAROM
product
(Continued)
⎯9.312.5
⎯7.09.5
⎯11.215.2
40
MB95120MB Series
(Continued)
(VCC = AVCC = 5.0 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
Parameter
Sym-bol
Pin name
ConditionFCL = 32 kHzFMPL = 128 kHzSub PLL mode (multiplied by 4) , TA = + 25 °CFCH = 10 MHz
Timebase timer modeTA = + 25 °CSub stop modeTA = + 25 °CFCH = 16 MHz
At operating of A/D conversion
AVCC
IAH
LCD internal division resistanceCOM0 to COM3 output impedance
FCH = 16 MHz
At stopping of A/D conversionTA = + 25 °C
⎯
Between V3 and VSS
Value
Min
Typ
Max
UnitRemarks
ICCSPLL
VCC
(External clock operation)
⎯160400µA
ICTS
Power supply current*2
ICCHIA
⎯⎯⎯
0.403.52.4
1.10204.7
mAµAmA
⎯15µA
RLCD⎯300⎯kΩ
RVCOMCOM0 to COM3V1 to V3 = 3.6 V⎯⎯5kΩ
SEG00 to
SEG39 output RVSEGimpedanceLCD leak current
ILCDL
SEG00 to SEG39V0 to V3,
COM0 to COM3SEG00 to SEG39
⎯⎯⎯7kΩ
⎯ − 1⎯ + 1µA
*1 : Product without clock supervisor only.
*2 : •The power-supply current is determined by the external clock. When both low voltage detection option and
clock supervisor are selected, the power-supply current will be a value of adding current consumption of the low voltage detection circuit (ILVD) and current consumption of built-in CR oscillator (ICSV) to the specified value.•Refer to “4. AC Characteristics (1) Clock Timing” for FCH and FCL.
•Refer to “4. AC Characteristics (2) Source Clock/Machine Clock” for FMP and FMPL.
41
MB95120MB Series
4.AC Characteristics
(1) Clock Timing
(VCC = 2.42 V to 5.5 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
Parameter
Sym-Condi-Pin nameboltion
Value
Min1.001.00
FCH
Clock frequency
X0, X1
3.003.003.003.00⎯
FCL
X0A, X1A
⎯
tHCYL
Clock cycle time
tLCYLtWH1tWL1tWH2tWL2tCRtCF
X0A, X1A
X0X0AX0, X0AX0, X1
⎯61.530.8⎯61.5⎯⎯
32.768⎯⎯30.5⎯15.2⎯
⎯10001000⎯⎯⎯5
kHznsns µsns µsns
Typ⎯⎯⎯⎯⎯⎯32.768
Max16.2532.5010.008.136.504.06⎯
UnitMHz
Remarks
When using main oscillation circuit
MHzWhen using external clockMHzMain PLL multiplied by 1MHzMain PLL multiplied by 2MHzMain PLL multiplied by 2.5MHzMain PLL multiplied by 4kHz
When using sub oscillation circuitWhen using sub PLLVCC = 2.3 V to 3.6 VWhen using main oscilla-tion circuit
When using external clockWhen using sub oscilla-tion circuit
When using external clockDuty ratio is about 30% to 70%.
When using external clock
Input clock pulse width
Input clock rise time and fall time
42
MB95120MB Series
• Input wave form for using external clock (main clock) tHCYLtWH1tCRtCF0.8 VCC0.8 VCC0.2 VCC0.2 VCC0.2 VCCtWL1X0• Figure of Main Clock Input Port External ConnectionWhen using a crystal or ceramic oscillatorMicrocontrollerX0X1FCHC1C2When using external clockMicrocontrollerX0X1OpenFCH• Input wave form for using external clock (sub clock) tLCYLtWH2tCRtCF0.8 VCC0.8 VCC0.2 VCC0.2 VCC0.2 VCCtWL2X0A• Figure of Sub clock Input Port External ConnectionWhen using a crystal or ceramic oscillatorMicrocontrollerX0AX1AFCLC1C2When using external clockMicrocontrollerX0AX1AOpenFCL43
MB95120MB Series
(2) Source Clock/Machine Clock
(VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
Parameter
Symbol
Condi-tion
ValueMin61.5
Source clock cycle time*1 (Clock before setting division)
tSCLK
7.6
FSPFSPL
⎯
0.5016.38461.5
tMCLK
7.6
FMPFMPL
0.0311.024
976.516.250131.072
µs
61.016.25131.07232000
µs
Max2000
Unit
Remarks
When using main clockMin : FCH = 8.125 MHz, PLL multiplied by 2
Max : FCH = 1 MHz, divided by 2When using sub clockMin : FCL = 32 kHz, PLL multiplied by 4
Max : FCL = 32 kHz, divided by 2
ns
Source clock frequency
MHzWhen using main clockkHzWhen using sub clockns
When using main clock
Min : FSP = 16.25 MHz, no divisionMax : FSP = 0.5 MHz, divided by 16When using sub clock
Min : FSPL = 131 kHz, no divisionMax : FSPL = 16 kHz, divided by 16
Machine clock cycle time*2 (Minimum instruction execution time)
Machine clock frequency
MHzWhen using main clockkHzWhen using sub clock
*1 : Clock before setting division due to machine clock division ratio selection bit (SYCC : DIV1 and DIV0) . This
source clock is divided by the machine clock division ratio selection bit (SYCC : DIV1 and DIV0) , and it becomes the machine clock. Further, the source clock can be selected as follows.•Main clock divided by 2
•PLL multiplication of main clock (select from 1, 2, 2.5, 4 multiplication) •Sub clock divided by 2
•PLL multiplication of sub clock (select from 2, 3, 4 multiplication) *2 : Operation clock of the microcontroller. Machine clock can be selected as follows.
•Source clock (no division) •Source clock divided by 4•Source clock divided by 8•Source clock divided by 16• Outline of clock generation blockFCH(main oscillation)Divided by 2Main PLL× 1× 2× 2.5× 4SCLK(source clock)FCL(sub oscillation)Divided by 2Clock mode select bit(SYCC: SCS1, SCS0)Divisioncircuit× 1× 1/4× 1/8× 1/16MCLK(machine clock)Sub PLL× 2× 3× 444
MB95120MB Series
• Operating voltage - Operating frequency (TA = − 40 °C to + 105 °C) •MB95F124MB/F124NB/F124JB/F126MB/F126NB/F126JB/F128MB/F128NB/F128JBMain clock mode and main PLL mode operation guarantee range5.5Sub PLL, sub clock mode and watch mode operation guarantee range5.5Operating voltage (V) Operating voltage (V) 3.52.4216.384 kHz32 kHz131.072 kHz2.420.5 MHz3 MHz10 MHz16.25 MHzPLL operation guarantee rangePLL operation guarantee rangeMain clock operation guarantee rangeSource clock frequency (FSPL) Source clock frequency (FSP) • Operating voltage - Operating frequency (TA = + 5 °C to + 35 °C) •MB95FV100D-103Sub PLL, sub clock mode and watch mode operation guarantee range5.55.5Main clock mode and main PLL mode operation guarantee rangeOperating voltage (V) Operating voltage (V) 3.52.72.716.384 kHz32 kHz131.072 kHz0.5MHz3 MHz10 MHz16.25 MHzPLL operation guarantee rangePLL operation guarantee rangeMain clock operation guarantee rangeSource clock frequency (FSPL) Source clock frequency (FSP) 45
MB95120MB Series
• Main PLL operation frequency[MHz]16.251615 × 412 Source clock frequency (Fsp) × 2.510 × 2 × 17.5 6 5 3 0 3 4 4.062 5 6.4 6.5 [MHz]8 8.125 10 Machine clock frequency (FMP) 46
MB95120MB Series
(3) External Reset
(VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
Parameter
Symbol
Pin Condi-nametion
ValueMin2 tMCLK*1
RST “L” levelpulse width
tRSTL
RST⎯
Oscillation time of oscillator*2 + 100
100
*1 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
*2 : Oscillation start time of oscillator is the time that the amplitude reaches 90 %. In the crystal oscillator, the
oscillation time is between several ms and tens of ms. In ceramic oscillators, the oscillation time is between hundreds of µs and several ms. In the external clock, the oscillation time is 0 ms.
• At normal operatingtRSTLMax⎯⎯⎯
Unitnsµs
Remarks
At normal operating
At stop mode, sub clock mode, sub sleep mode, and watch modeAt timebase timer mode
RST0.2 VCC0.2 VCC• At stop mode, sub clock mode, sub sleep mode, watch mode, and power-onRST90% of amplitudetRSTL0.2 VCC0.2 VCCX0Internal operating clockOscillation time Oscillation stabilization wait timeof oscillatorExecute instructionInternal reset100 µs47
MB95120MB Series
(4) Power-on Reset
(AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
Parameter
Power supply rising timePower supply cutoff time
SymboltRtOFF
VCCPin name
Condition
⎯⎯
ValueMin⎯1
Max50⎯
Unitmsms
Waiting time until power-on
Remarks
tR2.5 VtOFFVCC0.2 V0.2 V0.2 VNote : Sudden change of power supply voltage may activate the power-on reset function. When changing power
supply voltages during operation, set the slope of rising within 30 mV/ms as shown below.
VCC2.3 VLimiting the slope of rising within 30 mV/ms is recommended.Hold Condition in stop modeVSS48
MB95120MB Series
(5) Peripheral Input Timing
(VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
Parameter
Peripheral input “H” pulse widthPeripheral input “L” pulse width
Symbol
tILIH
Pin nameINT00 to INT07, INT10 to INT13, EC0, EC1, TI0, TRG0/ADTG,
TRG1
Condition
ValueMin2 tMCLK*
Max⎯⎯
Unitnsns
⎯
2 tMCLK*
tIHIL
* : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
tILIHtIHILINT00 to INT07,INT10 to INT13, EC0, EC1,TI0, TRG0/ADTG, TRG10.8 VCC0.8 VCC0.2 VCC0.2 VCC49
MB95120MB Series
(6) UART/SIO, Serial I/O Timing
(VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
Parameter
Serial clock cycle timeUCK ↓ → UO timeValid UI → UCK ↑
UCK ↑ → valid UI hold timeSerial clock “H” pulse widthSerial clock “L” pulse widthUCK ↓ → UO timeValid UI → UCK ↑
UCK ↑ → valid UI hold time
SymboltSCYCtSLOVtIVSHtSHIXtSHSLtSLSHtSLOVtIVSHtSHIX
Pin nameUCK0UCK0, UO0UCK0, UI0UCK0, UI0UCK0UCK0UCK0, UO0UCK0, UI0UCK0, UI0
External clock operation output pin : CL = 80 pF + 1TTL.Internal clock operation output pin : CL = 80 pF + 1TTL.
Condition
ValueMin4 tMCLK* − 1902 tMCLK*2 tMCLK*4 tMCLK*4 tMCLK*02 tMCLK*2 tMCLK*
Max⎯+190⎯⎯⎯⎯190⎯⎯
Unitnsnsnsnsnsnsnsnsns
* : Refer to “ (2) Source Clock/Machine Clock” for tMCLK. •Internal shift clock modetSCYCUCK00.8 VtSLOV2.4 V0.8 VUO02.4 V0.8 VtIVSHtSHIX0.8 VCC0.2 VCCUI00.8 VCC0.2 VCC•External shift clock modetSLSHtSHSL0.8 VCC0.8 VCC0.2 VCC0.2 VCCtSLOVUCK0UO02.4 V0.8 VtIVSHtSHIX0.8 VCC0.2 VCCUI00.8 VCC0.2 VCC50
MB95120MB Series
(7) LIN-UART Timing
Sampling at the rising edge of sampling clock*1 and prohibited serial clock delay*2 (ESCR register : SCES bit = 0, ECCR register : SCDE bit = 0)
(VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = −40 °C to + 105 °C)
Parameter
Serial clock cycle timeSCK ↓ → SOT delay timeValid SIN → SCK ↑
SCK ↑ → valid SIN hold timeSerial clock “L” pulse widthSerial clock “H” pulse widthSCK ↓ → SOT delay timeValid SIN → SCK ↑
SCK ↑ → valid SIN hold timeSCK fall timeSCK rise time
Sym-Pin nameboltSCYCtSLOVItIVSHItSHIXItSLSHtSHSLtIVSHEtSHIXEtFtR
SCKSCK, SOT
Condition
Value
Min5 tMCLK*3
Max⎯+95⎯⎯⎯⎯2 tMCLK*3 + 95
⎯⎯1010
Unitnsnsnsnsnsnsnsnsnsnsns
Internal clock −95operation output pin :
SCK, SINCL = 80 pF + 1 TTL.tMCLK*3 + 190SCK, SIN0SCKSCK
External clock SCK, SINoperation output pin :
CL = 80 pF + 1 TTL.
SCK, SINSCKSCK
3 tMCLK*3 − tRtMCLK*3 + 95
⎯190tMCLK*3 + 95
⎯⎯
tSLOVESCK, SOT
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
51
MB95120MB Series
•Internal shift clock modetSCYC2.4 V0.8 VtSLOVI2.4 V 0.8 VtIVSHItSHIXI0.8 VSCK SOTSIN0.8 VCC0.8 VCC0.2 V CC0.2 VCC•External shift clock modetSLSHtSHSL0.8 V CC0.2 VCCtR0.8 VCCSCK0.8 VCC0.2 VCCtFtSLOVE2.4 V 0.8 VtIVSHESOT tSHIXE SIN0.8 VCC0.8 VCC0.2 VCC0.2 VCC52
MB95120MB Series
Sampling at the falling edge of sampling clock*1 and prohibited serial clock delay*2 (ESCR register : SCES bit = 1, ECCR register : SCDE bit = 0)
(VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = −40 °C to + 105 °C)
Parameter
Serial clock cycle timeSCK ↑ → SOT delay timeValid SIN → SCK ↓
SCK ↓ → valid SIN hold timeSerial clock “H” pulse widthSerial clock “L” pulse widthSCK ↑ → SOT delay timeValid SIN → SCK ↓
SCK ↓ → valid SIN hold timeSCK fall timeSCK rise time
Sym-boltSCYCtSHOVItIVSLItSLIXItSHSLtSLSHtSHOVEtIVSLEtSLIXEtFtR
Pin nameSCKSCK, SOT
Internal clock operation output pin :
SCK, SINCL = 80 pF + 1 TTL.SCK, SINSCKSCKSCK, SOT
External clock
SCK, SINoperation output pin : SCK, SINCL = 80 pF + 1 TTL.SCKSCK
Condition
Value
Min5 tMCLK*3
−95tMCLK*3 + 190
03 tMCLK*3 − tRtMCLK*3 + 95
⎯190tMCLK*3 + 95
⎯⎯
Max⎯+95⎯⎯⎯⎯2 tMCLK*3 + 95
⎯⎯1010
Unitnsnsnsnsnsnsnsnsnsnsns
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
53
MB95120MB Series
•Internal shift clock modetSCYCSCK 2.4 V tSHOVI2.4 V 0.8 VtIVSLItSLIXI0.8 V2.4 VSOTSIN0.8 VCC0.8 VCC0.2 V CC0.2 VCC•External shift clock modetSHSLtSLSH0.8 VCC0.2 VCC0.2 VCCSCK0.2 VCCtR0.8 VCCtSHOVE2.4 V 0.8 VtFSOTtIVSLE tSLIXE SIN0.8 VCC0.8 VCC0.2 VCC0.2 VCC54
MB95120MB Series
Sampling at the rising edge of sampling clock*1 and enabled serial clock delay*2 (ESCR register : SCES bit = 0, ECCR register : SCDE bit = 1)
(VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = −40 °C to + 105 °C)
Parameter
Serial clock cycle timeSCK ↑ → SOT delay timeValid SIN → SCK ↓SCK ↓ → valid SIN hold timeSOT → SCK ↓ delay time
Sym-boltSCYCtSHOVItIVSLItSLIXItSOVLI
Pin nameSCKSCK, SOTSCK, SINSCK, SINSCK, SOT
Condition
ValueMin5 tMCLK*3
−95Internal clock
operation output pin : tMCLK*3 + 190CL = 80 pF + 1 TTL.
0
⎯
Max⎯+95⎯⎯4 tMCLK*3
Unitnsnsnsnsns
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK. tSCYCSCKtSOVLI2.4 V0.8 V2.4 V 0.8 V tIVSLItSLIXI0.8 VCC0.2 VCCtSHOVI2.4 V0.8 V 0.8 VSOTSIN0.8 VCC0.2 VCC55
MB95120MB Series
Sampling at the falling edge of sampling clock*1 and enabled serial clock delay*2 (ESCR register : SCES bit = 1, ECCR register : SCDE bit = 1)
(VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = −40 °C to + 105 °C)
Parameter
Serial clock cycle timeSCK ↓ → SOT delay timeValid SIN → SCK ↑
SCK ↑ → valid SIN hold timeSOT → SCK ↑ delay time
Sym-boltSCYCtSLOVItIVSHItSHIXItSOVHI
Pin nameSCKSCK, SOT
Condition
ValueMin5 tMCLK*3
Max⎯+95⎯⎯4 tMCLK*3
Unitnsnsnsnsns
−95Internal clock
SCK, SINoperating output pin : tMCLK*3 + 190
CL = 80 pF + 1 TTL.
SCK, SIN0
⎯
SCK, SOT
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.tSCYCSCKtSOVHI2.4 V0.8 VtSLOVI2.4 V0.8 V tIVSHItSHIXI0.8 VCC0.2 VCC2.4 V 0.8 V 0.8 VCC0.2 VCC2.4 VSOTSIN56
MB95120MB Series
(8) I2C Timing
(VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
Value
Parameter
SCL clock frequency
(Repeat) Start condition hold time SDA ↓ → SCL ↓ SCL clock “L” widthSCL clock “H” width
(Repeat) Start condition setup time SCL ↑ → SDA ↓
Data hold time SCL ↓ → SDA ↓ ↑Data setup time SDA ↓ ↑ → SCL ↑Stop condition setup time SCL ↑ → SDA ↑
Bus free time between stop condition and start condition
SymbolfSCLtHD;STAtLOWtHIGHtSU;STAtHD;DATtSU;DATtSU;STOtBUF
Pin nameSCL0SCL0SDA0SCL0SCL0SCL0SDA0SCL0SDA0SCL0SDA0SCL0SDA0SCL0SDA0
R = 1.7 kΩ, C = 50 pF*1Condition
Standard-modeMin04.04.74.04.700.25*44.04.7
Max100⎯⎯⎯⎯3.45*2⎯⎯⎯
Fast-modeMin00.61.30.60.600.1*40.61.3
Max400⎯⎯⎯⎯0.9*3⎯⎯⎯
kHz µsµs µs µs µs µs µs µsUnit
*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*2 : The maximum tHD;DAT have only to be met if the device dose not stretch the “L” width (tLOW) of the SCL signal.*3 : A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement
tSU;DAT ≥ 250 ns must then be met.*4 : Refer to “ • Note of SDA and SCL set-up time”.• Note of SDA and SCL set-up timeSDA0Input data set-up timeSCL06 tcpNote : The rating of the input data set-up time in the device connected to the bus cannot be satisfied depending on
the load capacitance or pull-up resistor.
Be sure to adjust the pull-up resistor of SDA and SCL if the rating of the input data set-up time cannot besatisfied.
57
MB95120MB Series
tWAKEUPSDA0tLOWSCL0tHD;STAtSU;DATtSU;STAtSU;STOtHD;DATtHIGHtHD;STAtBUF58
MB95120MB Series
(VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = −40 °C to + 105 °C)
ParameterSCL clock “L” widthSCL clock “H” width
Sym-Pin
Condition
bolnametLOWtHIGH
SCL0SCL0
Value*2
Min
(2 + nm / 2) tMCLK − 20 (nm / 2) tMCLK − 20
Max⎯
(nm / 2 ) tMCLK + 20
Unitnsns
RemarksMaster modeMaster modeMaster mode
Maximum value is applied when m, n = 1, 8.
Otherwise, the minimum value is applied.Master modeMaster mode
Start condition SCL0
tHD;STA
hold timeSDA0
(−1 + nm / 2) tMCLK − 20 (−1 + nm) tMCLK + 20ns
Stop condition SCL0
tSU;STO
setup timeSDA0Start condition SCL0
tSU;STA
setup timeSDA0Bus free time between stop condition and start condition
tBUF
SCL0SDA0SCL0SDA0
R = 1.7 kΩ, C = 50 pF*1
(1 + nm / 2) tMCLK − 20 (1 + nm / 2) tMCLK + 20 (1 + nm / 2) tMCLK − 20 (1 + nm / 2) tMCLK + 20
nsns
(2 nm + 4) tMCLK − 20⎯ns
Data hold timetHD;DAT3 tMCLK − 20⎯nsMaster modeMaster modeWhen assuming that “L” of SCL is not extended, the minimum value is applied to first bit of continuous data.
Otherwise, the maximum value is applied.Minimum value is applied to interrupt at 9th SCL↓.
Maximum value is applied to interrupt at 8th SCL↓.At receptionAt receptionUndetected when 1 tMCLK is used at reception
(Continued)
59
Data setup time
tSU;DAT
SCL0SDA0
(−2 + nm / 2) tMCLK − 20 (−1 + nm / 2) tMCLK + 20ns
Setup time between clearing
interrupt and SCL risingSCL clock “L” width
SCL clock “H” width
tSU;INTSCL0 (nm / 2) tMCLK − 20 (1 + nm / 2) tMCLK + 20ns
tLOWtHIGH
SCL0SCL0
4 tMCLK − 204 tMCLK − 20
⎯⎯⎯
nsnsns
Start condition SCL0
tHD;STA
detectionSDA0
2 tMCLK − 20
MB95120MB Series
(Continued)
(VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = −40 °C to + 105 °C)
ParameterStop condition detection
Restart condition detection conditionBus free timeData hold timeData setup timeData hold timeData setup timeSDA↓→SCL↑
(at wakeup function)
Sym-Pin
Condition
bolnametSU;STO
SCL0SDA0SCL0SDA0SCL0SDA0
SCL0
SDA0R = 1.7 kΩ,
1
SCL0C = 50 pF*SDA0SCL0SDA0SCL0SDA0SCL0SDA0
Value*2
Min
2 tMCLK − 20
Max⎯
UnitRemarksUndetected when 1 tMCLK is used at reception
Undetected when 1 tMCLK is used at receptionAt reception
At slave transmission mode
At slave transmission modeAt receptionAt reception
ns
tSU;STAtBUFtHD;DATtSU;DATtHD;DATtSU;DATtWAKE-UP
2 tMCLK − 20⎯⎯⎯⎯⎯⎯
nsnsnsnsnsns
2 tMCLK − 202 tMCLK − 20tLOW − 3 tMCLK − 20
0tMCLK − 20Oscillation stabilization wait time + 2 tMCLK − 20
⎯ns
*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.*2 : •
•••
Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
m is CS4 bit and CS3 bit (bit 4 and bit 3) of I2C clock control register (ICCR) .n is CS2 bit to CS0 bit (bit 2 to bit 0) of I2C clock control register (ICCR) .
Actual timing of I2C is determined by m and n values set by the machine clock (tMCLK) and CS4 to CS0 of ICCR0 register.•Standard-mode :
m and n can be set at the range : 0.9 MHz < tMCLK (machine clock) < 10 MHz.Setting of m and n determines the machine clock that can be used below. (m, n) = (1, 8) : 0.9 MHz < tMCLK ≤ 1 MHz (m, n) = (1, 22) , (5, 4) , (6, 4) , (7, 4) , (8, 4) : 0.9 MHz < tMCLK ≤ 2 MHz (m, n) = (1, 38) , (5, 8) , (6, 8) , (7, 8) , (8, 8) : 0.9 MHz < tMCLK ≤ 4 MHz (m, n) = (1, 98) : 0.9 MHz < tMCLK ≤ 10 MHz•Fast-mode :
m and n can be set at the range : 3.3 MHz < tMCLK (machine clock) < 10 MHz.Setting of m and n determines the machine clock that can be used below. (m, n) = (1, 8) : 3.3 MHz < tMCLK ≤ 4 MHz (m, n) = (1, 22) , (5, 4) : 3.3 MHz < tMCLK ≤ 8 MHz (m, n) = (6, 4) : 3.3 MHz < tMCLK ≤ 10 MHz
60
MB95120MB Series
(9) Low Voltage Detection
(AVss = Vss = 0.0 V, TA = −40 °C to + 105 °C)
Parameter
Release voltageDetection voltageHysteresis width
Power-supply start voltagePower-supply end voltagePower-supply voltage change time
(at power supply rise)
SymbolVDL+VDL-VHYSVoffVon
Condi-tion
Value
Min2.522.4270⎯4.90.3
tr
⎯
Power-supply voltage change time
(at power supply fall)Reset release delay timeReset detection delay timeCurrent consumption
⎯300
tf
⎯
td1td2ILVD
⎯⎯⎯
300⎯⎯38
⎯4003050
3000⎯
⎯⎯
Typ2.702.60100⎯⎯⎯
Max2.882.78⎯2.3⎯⎯
UnitVVmVVVµs
Slope of power supply that reset release signal generates
Remarks
At power-supply riseAt power-supply fall
Slope of power supply that reset µs release signal generates within
rating (VDL+)µs
Slope of power supply that reset detection signal generates
Slope of power supply that reset µs detection signal generates with-in rating (VDL-)µs µs µA
Current consumption of low voltage detection circuit only
VCCVonVoffVCCtftrtimeVDL+VDL-VHYSInternal reset signaltime61
td2td1MB95120MB Series
(10) Clock Supervisor Clock
(Vcc = AVcc = 5 V ± 10%, AVss = Vss = 0.0 V, TA = −40 °C to + 105 °C)
ParameterOscillation frequencyOscillation start timeCurrent consumption
SymbolfOUTtwk
⎯
ICSV
⎯
20
36
µA
Condi-tion
Value
Min50⎯
Typ100⎯
Max20010
UnitkHz µs
Current consumption of built-in CR oscillator, at 100 kHz oscillation
Remarks
62
MB95120MB Series
5.A/D Converter
(1) A/D Converter Electrical Characteristics
(AVcc = Vcc = 4.0 V to 5.5 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 105 °C)
ParameterResolutionTotal errorLinearity errorDifferential linear errorZero transition voltageFull-scale transition voltage
VOTVFST⎯Symbol
Condi-tion
Value
Min⎯ − 3.0 − 2.5 − 1.9AVss − 1.5 LSBAVR − 3.5 LSB0.9
Compare time
⎯
1.8
⎯
Sampling time
⎯
1.2
Analog input currentAnalog input voltageReference voltage
IAINVAIN⎯IRIRH
−0.3AVssAVss + 4.0
⎯⎯
⎯⎯⎯⎯600⎯
∞+0.3AVRAVcc9005
µsµAVVµAµA
AVR pinAVR pin, During A/D operationAVR pin, At stop mode
⎯
16500
µs
Typ⎯⎯⎯⎯AVss + 0.5 LSBAVR − 1.5 LSB⎯
Max10 + 3.0 + 2.5 + 1.9AVss + 2.5 LSBAVR + 0.5 LSB16500
UnitbitLSBLSBLSBVVµs
4.5 V ≤ AVcc ≤ 5.5 V
4.0 V ≤ AVcc < 4.5 V
4.5 V ≤ AVcc ≤ 5.5 V,
At external
impedance < 5.4 kΩ4.0 V ≤ AVcc < 4.5 V,
At external
impedance < 2.4 kΩ
Remarks
0.6⎯∞µs
Reference voltagesupply current
63
MB95120MB Series
(2) Notes on Using A/D Converter
• About the external impedance of analog input and its sampling time
A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting A/D conversion precision. Therefore to satisfy the A/D conversion precision standard, consider the relationshipbetween the external impedance and minimum sampling time and either adjust the register value and operatingfrequency or decrease the external impedance so that the sampling time is longer than the minimum value. Also,if the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.• Analog input equivalent circuitRAnalog inputCComparatorDuring sampling : ON4.5 V ≤ AVcc ≤ 5.5 V4.0 V ≤ AVcc < 4.5 VNote : The values are reference values.R2.0 kΩ (Max) 8.2 kΩ (Max) C16 pF (Max) 16 pF (Max) • The relationship between external impedance and minimum sampling time(External impedance = 0 kΩ to 100 kΩ)1009080706050403020100024(External impedance = 0 kΩ to 20 kΩ)201816141210864200External impedance [kΩ]External impedance [kΩ]AVCC ≥ 4.5 VAVCC ≥ 4.5 VAVCC ≥ 4.0 VAVCC ≥ 4.0 V681012141234Minimum sampling time [µs]Minimum sampling time [µs]• About errors
As |AVCC − AVSS| becomes smaller, values of relative errors grow larger.
64
MB95120MB Series
(3) Definition of A/D Converter Terms•Resolution
The level of analog variation that can be distinguished by the A/D converter.When the number of bits is 10, analog voltage can be divided into 210 = 1024.•Linearity error (unit : LSB)
The deviation between the value along a straight line connecting the zero transition point (“00 0000 0000” ← → “00 0000 0001”) of a device and the full-scale transition point
(“11 1111 1111” ← → “11 1111 1110”) compared with the actual conversion values obtained.•Differential linear error (Unit : LSB)
Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value.•Total error (unit: LSB)
Difference between actual and theoretical values, caused by a zero transition error, full-scale transition error,linearity error, quantum error, and noise.
Ideal I/O characteristicsVFSTTotal error3FFH3FEH3FFH3FEHDigital outputDigital output3FDH1.5 LSB 3FDHActual conversion characteristic{1 LSB × (N − 1) + 0.5 LSB}004H003H002H001HAVSSVOT1 LSB0.5 LSB004H003H002H001HVNTActual conversion characteristicIdeal characteristicsAnalog inputAVR − AVSS1024 (V) AVRAVSSAnalog inputAVR1 LSB =Total error ofVNT − {1 LSB × (N − 1) + 0.5 LSB} = [LSB]digital output N1 LSBN : A/D converter digital output valueVNT : A voltage at which digital output transits from (N − 1)H to NH.(Continued)65
MB95120MB Series
(Continued)Zero transition error004HActual conversion characteristic Full-scale transition errorIdeal characteristics3FFHDigital output003HIdeal characteristicsActual conversion characteristicDigital outputActual conversion characteristic3FEHVFST (measurement value)Actual conversion characteristic002H3FDH001HVOT (measurement value)3FCHAVRAVSSAVSSAVRAnalog inputAnalog inputLinearity error3FFH3FEH3FDHActual conversion characteristic Differential linear errorIdeal characteristics(N+1)H{1 LSB × N + VOT}VFST (measurement value)Actual conversion characteristicDigital outputDigital outputV (N+1)TNHVNT004H003H002H001HVOT (measurement value)Actual conversion characteristicIdeal characteristics(N-1)HVNTActual conversion characteristic(N-2)H AVRAVSSAVSSAnalog inputAnalog inputAVRLinear error in = VNT − {1 LSB × N + VOT}1 LSBdigital output NDifferential linear error = V (N + 1) T − VNT1 LSBin digital output N − 1N : A/D Converter digital output valueVNT : A voltage at which digital output transits from (N − 1)H to NH.VOT (Ideal value) = AVSS + 0.5 LSB [V]VFST (Ideal value) = AVR − 1.5 LSB [V]66
MB95120MB Series
6.Flash Memory Program/Erase Characteristics
Parameter
Sector erase time (4 Kbytes sector) Sector erase time (16 Kbytes sector) Byte programming timeProgram/erase cyclePower supply voltage at program/erase
Flash memory data retention time
*1 : TA = + 25 °C, VCC = 5.0 V, 10000 cycles*2 : TA = + 85 °C, VCC = 4.5 V, 10000 cycles
*3 : This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at +85 °C) .
⎯Condition
Value
Min⎯⎯⎯100004.520*3
Typ0.2*10.5*132⎯⎯⎯
Max0.5*27.5*23600⎯5.5⎯
UnitssµscycleVyear
Average TA = +85 °C
Remarks
Excludes 00H programming prior erasure.
Excludes 00H programming prior erasure.
Excludes system-level overhead.
67
MB95120MB Series
■EXAMPLE CHARACTERISTICS
• Power supply current temperatureICC − VCCTA = + 25 °C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2) Main clock mode, at external clock operating20ICC − TAVCC = 5.5 V, FMP = 10, 16 MHz (divided by 2) Main clock mode, at external clock operating20FMP = 16 MHz15ICC [mA]FMP = 16 MHzICC [mA]1510FMP = 10 MHzFMP = 8 MHz10FMP = 10 MHz5FMP = 4 MHzFMP = 2 MHz50234VCC [V]5670−500+50TA [°C]+100+150ICCS − VCCTA = + 25 °C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2) Main sleep mode, at external clock operating20ICCS − TAVCC = 5.5 V, FMP = 10, 16 MHz (divided by 2) Main sleep mode, at external clock operating2015ICCS [mA]ICCS [mA]1510FMP = 16 MHz5FMP = 10 MHzFMP = 8 MHzFMP = 4 MHzFMP = 2 MHz234VCC [V]56710FMP = 16 MHz5FMP = 10 MHz00−500+50TA [°C]+100+150ICCMPLL − VCCTA = + 25 °C, FMP = 2, 4, 8, 10, 16 MHz (Multiply-by-2.5) Main PLL mode, at external clock operating20ICCMPLL − TAVCC = 5.5 V, FMP = 10, 16 MHz (Multiply-by-2.5) Main PLL mode, at external clock operating2015ICCMPLL [mA]ICCMPLL [mA]15FMP = 16 MHzFMP = 16 MHz10FMP = 10 MHzFMP = 8 MHz10FMP = 10 MHz5FMP = 4 MHzFMP = 2 MHz50234VCC [V]5670−500+50TA [°C]+100+150(Continued)68
MB95120MB Series
ICCL − VCCTA = + 25 °C, FMPL = 16 kHz (divided by 2) Sub clock mode, at external clock operating100ICCL − TAVCC = 5.5 V, FMPL = 16 kHz (divided by 2) Sub clock mode, at external clock operating1007575ICCL [µA]ICCL [µA]505025250234VCC [V]5670−500+50TA [°C]+100+150ICCLS − VCCTA = + 25 °C, FMPL = 16 kHz (divided by 2) Sub sleep mode, at external clock operating100ICCLS − TAVCC = 5.5 V, FMPL = 16 kHz (divided by 2) Sub sleep mode, at external clock operating1007575ICCLS [µA]ICCLS [µA]505025250234VCC [V]5670−500+50TA [°C]+100+150ICCT − VCCTA = + 25 °C, FMPL = 16 kHz (divided by 2) Clock mode, at external clock operating100ICCT − TAVCC = 5.5 V, FMPL = 16 kHz (divided by 2) Clock mode, at external clock operating1007575ICCT [µA]ICCT [µA]505025250234VCC [V]5670−500+50TA [°C]+100+150(Continued)69
MB95120MB Series
ICCSPLL − VCCTA = + 25 °C, FMPL = 128 kHz (Multiply-by-4) Sub PLL mode, at external clock operating100ICCSPLL − TAVCC = 5.5 V, FMPL = 128 kHz (Multiply-by-4) Sub PLL mode, at external clock operating1007575ICCSPLL [µA]ICCSPLL [µA]505025250234VCC [V]5670−500+50TA [°C]+100+150ICTS − VCCTA = + 25 °C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2) Time-base timer mode, at external clock operating2.0ICTS − TAVCC = 5.5 V, FMP = 10, 16 MHz (divided by 2) Time-base timer mode, at external clock operating2.01.5FMP = 16 MHz1.5ICTS [mA]FMP = 16 MHzICTS [mA]1.0FMP = 10 MHzFMP = 8 MHz0.5FMP = 4 MHzFMP = 2 MHz0.0234VCC [V]5671.0FMP = 10 MHz0.50.0−500+50TA [°C]+100+150ICCH − VCCTA = + 25 °C, FMPL = (stop) Sub stop mode, at external clock stopping20ICCH − TAVCC = 5.5 V, FMPL = (stop) Sub stop mode, at external clock stopping201515ICCH [µA]ICCH [µA]1010550234VCC [V]5670−500+50TA [°C]+100+150(Continued)70
MB95120MB Series
(Continued)IA − AVCCTA = + 25 °C, FMP = 16 MHz (divided by 2) Main clock mode, at external clock operating4IA − TAVCC = 5.5 V, FMP = 16 MHz (divided by 2) Main clock mode, at external clock operating433IA [mA]IA [mA]22110234AVCC [V]5670−500+50TA [°C]+100+150IR − AVCCTA = + 25 °C, FMP = 16 MHz (divided by 2) Main clock mode, at external clock operating4IR − TAVCC = 5.5 V, FMP = 16 MHz (divided by 2) Main clock mode, at external clock operating433IR [mA]2IR [mA]2110234AVCC [V]5670−500+50TA [°C]+100+15071
MB95120MB Series
• Input voltageVIH1 − VCC and VIL − VCCTA = + 25 °C55VIHS1 − VCC and VILS − VCCTA = + 25 °C4VIH1VIH1 / VIL [V]4VIHS1 / VILS [V]VIHS13VIL23VILS2110234VCC [V]5670234VCC [V]567VIH2 − VCC and VIL − VCCTA = + 25 °C55VIHS2 − VCC and VILS − VCCTA = + 25 °C4VIHS2 / VILS [V]4VIH2VILVIHS2VIH2 / VIL [V]33VILS22110234VCC [V]5670234VCC [V]567VIHA − VCC and VILA − VCCTA = + 25 °C5VIHA4VILA3VIHM / VILM [V]VIHA / VILA [V]VIHM − VCC and VILM − VCCTA = + 25 °C543VIHM2VILM2110234VCC [V]5670234VCC [V]56772
MB95120MB Series
• Output voltage (VCC-VOH1) − IOHTA = + 25 °C2.7 V2.5 V3.3 V3.5 V3 V(VCC-VOH2) − IOHTA = + 25 °CVCC = 2.5 V1.00.8VCC = 4 VVCC = 4.5 VVCC = 5 VVCC = 5.5V1.0VCC = 2.45 V0.8VCC − VOH2 [V]VCC − VOH1 [V]VCC = 2.45 V0.60.40.20.00.60.40.20.0VCC = 2.7 VVCC = 3 VVCC = 3.3 VVCC = 3.5 VVCC = 4 VVCC = 4.5 VVCC = 5 VVCC = 5.5 V0−2−4−6IOH [mA]−8−100−2−4−6IOH [mA]−8−10VOL1 − IOL1TA = + 25 °C2.7 V3 VVOL2 − IOL2TA = + 25 °C1.00.80.6VCC = 2.45 V0.40.20.00246IOL1 [mA]810VCC = 3.3 VVCC = 3.5 V1.00.80.60.40.20.00.0VCC = 2.5 VVCC = 2.45 VVCC = 4 VVCC = 4.5 VVCC = 5 VVCC = 5.5VVCC = 2.5 VVCC = 2.7 VVCC = 3 VVCC = 3.3 VVCC = 3.5 VVCC = 4 VVCC = 4.5 VVCC = 5 VVCC = 5.5 V15.0VOL1 [V]VOL2 [V]2.55.07.510.0IOL2 [mA]12.5• Pull-upRPULL − VCCTA = + 25 °C250200RPULL [kΩ]150100500234VCC [V]5673
MB95120MB Series
■MASK OPTION
Part number
No.
Specifying procedure
Specify when ordering MASKMB95128MB
MB95F124MB/F124NB/F124JBMB95F126MB/126NB/F126JBMB95F128MB/F128NB/F128JB
Setting disabled
MB95FV100D-103Setting disabled
1
Clock mode select
• Single-system clock mode• Dual-system clock modeLow voltage detection reset*• With low voltage detection reset
• Without low voltage detection reset
Clock supervisor*
• With clock supervisor• Without clock supervisor
Dual-system clock
mode
Dual-system clock mode
Changing by the
switch on MCU boardChanging by the
switch on MCU boardChanging by the
switch on MCU boardMCU board switch set as following ;
• With supervisor :Without reset output
• Without supervisor :With reset outputFixed to oscillation stabilization wait time of (214−2) /FCH
2
Specify when ordering MASKSpecified by part
number
3
Specify when ordering MASKSpecified by part
number
4
Reset output*
• With reset output• Without reset output
Specify when ordering MASKSpecified by part
number
5
Oscillation stabilization wait time
Fixed to oscillation Fixed to oscillation
stabilization wait stabilization wait time oftime of (214−2) /FCH (214−2) /FCH
* : Refer to table below about clock mode select, low voltage detection reset, clock supervisor select and reset output.
74
MB95120MB Series
Part numberMB95128MBMB95F124MBMB95F124NBMB95F124JBMB95F126MBMB95F126NBMB95F126JBMB95F128MBMB95F128NBMB95F128JB
Clock mode selectLow voltage detection resetClock supervisorReset output
NoYesYesNoYesYesNoYesYesNoYesYesNo
NoNoYesNoNoYesNoNoYesNoNoYesNoNoYesNoNoYes
YesYesNoYesYesNoYesYesNoYesYesNoYesYesNoYesYesNo
Dual-system
Single-system
MB95FV100D-103
Dual-system
YesYesNoYesYes
75
MB95120MB Series
■ORDERING INFORMATION
Part number
MB95128MBPMCMB95F124MBPMCMB95F124NBPMCMB95F124JBPMCMB95F126MBPMCMB95F126NBPMCMB95F126JBPMCMB95F128MBPMCMB95F128NBPMCMB95F128JBPMCMB95128MBPFMB95F124MBPFMB95F124NBPFMB95F124JBPFMB95F126MBPFMB95F126NBPFMB95F126JBPFMB95F128MBPFMB95F128NBPFMB95F128JBPFMB2146-303A
(MB95FV100D-103PBT)
Package
100-pin plastic LQFP (FPT-100P-M20)
100-pin plastic QFP (FPT-100P-M06)
(
MCU board
224-pin plastic PFBGA (BGA-224P-M08)
)
76
MB95120MB Series
■PACKAGE DIMENSIONS
100-pin plastic LQFPLead pitchPackage width ×package lengthLead shapeSealing methodMounting heightWeight0.50 mm14.0 mm × 14.0 mmGullwingPlastic mold1.70 mm Max0.65 gP-LFQFP100-14×14-0.50(FPT-100P-M20)Code(Reference)100-pin plastic LQFP(FPT-100P-M20)16.00±0.20(.630±.008)SQNote 1)* : These dimensions do not include resin protrusion.Note 2)Pins width and pins thickness include plating thickness.Note 3)Pins width do not include tie bar cutting remainder.*14.00±0.10(.551±.004)SQ755176500.08(.003)Details of \"A\" partINDEX1.50–0.10.059–.004(Mounting height)26+0.20+.0081000.10±0.10(.004±.004)(Stand off)0.25(.010)0˚~8˚\"A\"(0.50(.020))0.60±0.15(.024±.006)1250.50(.020)0.20±0.05(.008±.002)0.08(.003)M0.145±0.055(.0057±.0022)C2005 FUJITSU LIMITED F100031S-c-2-1Dimensions in mm (inches).Note: The values in parentheses are reference valuesPlease confirm the latest Package dimension by following URL.http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
(Continued)
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MB95120MB Series
(Continued)
100-pin plastic QFPLead pitchPackage width ×package lengthLead shapeSealing methodMounting heightCode(Reference)0.65 mm14.00× 20.00 mmGullwingPlastic mold3.35 mm MAXP-QFP100-14×20-0.65(FPT-100P-M06)100-pin plastic QFP(FPT-100P-M06)23.90±0.40(.941±.016)*20.00±0.20(.787±.008)8051Note 1)* : These dimensions do not include resin protrusion.Note 2)Pins width and pins thickness include plating thickness.Note 3)Pins width do not include tie bar cutting remainder.81500.10(.004)17.90±0.40(.705±.016)*14.00±0.20(.551±.008)INDEXDetails of \"A\" part100311300.25(.010)+0.353.00–0.20+.014.118–.008(Mounting height)0~8˚0.17±0.06(.007±.002)0.65(.026)\"A\"0.32±0.05(.013±.002)0.13(.005)M0.80±0.20(.031±.008)0.88±0.15(.035±.006)0.25±0.20(.010±.008)(Stand off)C2002 FUJITSU LIMITED F100008S-c-5-5Dimensions in mm (inches).Note: The values in parentheses are reference values.Please confirm the latest Package dimension by following URL.http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
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MB95120MB Series
■MAIN CHANGES IN THIS EDITION
Page⎯2635
■ I/O MAP■ ELECTRICAL CHARACTERISTICS1. Absolute Maximum Ratings
Section⎯Change Results
Added the MB95128MB (MASK ROM product)Changed as follows for R/W of Reset source registerR → R/W
For the operating temperature, the max rating is changed;
+ 85 °C → + 105 °C
Changed as follows
TA = − 40 °C to + 85 °C → TA = − 40 °C to + 105 °CAdded “Main PLL multiplied by 4” in the Clock frequency• Changed in the remarks of source clock cycle time (when using main clock)
Min : FCH = 16.25 MHz, PLL multiplied by 1→ Min : FCH = 8.125 MHz, PLL multiplied by 2• Changed the footnote of *1;
PLL multiplication of main clock (select from 1, 2, 2.5 multiplication) →
PLL multiplication of main clock (select from 1, 2, 2.5, 4 multiplication)
• Added “ × 4” in the Main PLL of “• Outline of clock generation block“
Changed as follows
• Operating voltage − Operating frequency (TA = − 40 °C to + 85 °C) →
• Operating voltage − Operating frequency (TA = − 40 °C to + 105 °C)Changed the figure of • Main PLL operation frequency
(8) I2C Timing
■ EXAMPLE CHARACTERISTICS
Added the *4
Added the ■ EXAMPLE CHARACTERISTICS
37 to 42, 44, Temperature conditions on table47 to 51, 53, 55 to 57, 59 to 63
42
■ ELECTRICAL CHARACTERISTICS4. AC Characteristics (1) Clock Timing (2) Source Clock/Machine Clock
44
45
465768 to 73
The vertical lines marked in the left side of the page show the changes.
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MB95120MB Series
The information for microcontroller supports is shown in the following homepage.
http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
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