专利名称：BUS HAVING A DYNAMIC TIMING BRIDGE发明人：Craig D. Shaw,Matthew D. Akers,Robert N.
Ehrlich,Brett W. Murdock
申请号：US11461048申请日：20060731
公开号：US20080028253A1公开日：20080131
专利附图：
摘要：A data processing system may comprise an initiator device having an outputwhose timing is referenced by a clock input alone corresponding to a first delay along asignaling path. The exemplary data processing system further may further comprise a
target device having an input whose timing is referenced by a clock input alonecorresponding to a second delay along the signaling path and a system bus
interconnected between the initiator device and the target device within the signalingpath. The exemplary data processing system may further comprise a dynamic timingbridge coupled to the system bus within the signaling path, wherein responsive to acontrol signal representative of at least one system characteristic, the dynamic timingbridge performs one selected from the group consisting of (i) inserting a cyclic latencywithin the signaling path and (ii) not inserting the cyclic latency within the signaling path.
申请人：Craig D. Shaw,Matthew D. Akers,Robert N. Ehrlich,Brett W. Murdock
地址：Austin TX US,Austin TX US,Leander TX US,Round Rock TX US
国籍：US,US,US,US
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