PRELIMINARYCY7C1399D
256K (32K x 8) Static RAM
Features
•Pin- and function-compatible with CY7C1399B•Single 3.3V power supply
•Ideal for low-voltage cache memory applications•Highspeed—tAA = 8 ns
•Low active power
—ICC = 60 mA @ 10 ns•Low CMOS standby power—ISB2 = 1.2 mA (“L” Version only)•Data Retention at 2.0V
•Available in 28-SOJ and 28-TSOP I Pb-Free packages
Functional Description[1]
The CY7C1399D is a high-performance 3.3V CMOS StaticRAM organized as 32,768 words by 8 bits. Easy memoryexpansion is provided by an active LOW Chip Enable (CE) andactive LOW Output Enable (OE) and tri-state drivers. Thedevice has an automatic power-down feature, reducing thepower consumption when deselected.
An active LOW Write Enable signal (WE) controls thewriting/reading operation of the memory. When CE and WEinputs are both LOW, data on the eight data input/output pins(I/O0 through I/O7) is written into the memory locationaddressed by the address present on the address pins (A0through A14). Reading the device is accomplished by selectingthe device and enabling the outputs, CE and OE active LOW,while WE remains inactive or HIGH. Under these conditions,the contents of the location addressed by the information onaddress pins is present on the eight data input/output pins.The input/output pins remain in a high-impedance state unlessthe chip is selected, outputs are enabled, and Write Enable(WE) is HIGH. The CY7C1399D is available in 28-pin standard300-mil-wide SOJ and TSOP Type I Pb-Free packages.
Logic Block Diagram
PinConfigurations
SOJTop View
A5A6A7A8A9A10A11A12A13A14I/O0I/O1I/O2GND
1234567891011121314
2827262524232221201918171615
VCCWEA4A3A2A1OEA0CEI/O7I/O6I/O5I/O4I/O3
INPUTBUFFERI/O0I/O1A0A1A2A3A4A5A6A7A8A9CEWEOEROW DECODERI/O2SENSE AMPS32Kx8ARRAYI/O3I/O4I/O5COLUMNDECODERPOWERDOWNI/O6I/O7A10A11A12A13Note:
1.For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
A14CypressSemiconductorCorporationDocument #: 38-05467 Rev. *C
•3901NorthFirstStreet•
SanJose,CA 95134•408-943-2600
Revised January 10, 2005
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PRELIMINARY
CY7C1399D
1399D-12
1399D-15
UnitSelection Guide
1399D-10
Maximum Access Time
101215Maximum Operating Current
605040Maximum CMOS Standby Current
3.03.03.0L
1.2
1.2
1.2
Pin Configuration
Top View
TSOP IOE2221AA012320ACE2419A2I/O18A325I/O72617I/O6WE42716I/O5VCC2815I/O4AA5114GND3213I/OA63A712I/O2411I/O1510AA89A0A1069A1411
7
8
A1312
Document #: 38-05467 Rev. *CnsmAmA
Page 2 of 10
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PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guide-lines, not tested.)
Storage Temperature .................................–65°C to +150°CAmbient Temperature with
Power Applied.............................................–55°C to +125°CSupply Voltage on VCC to Relative GND
[2]
CY7C1399D
DC Input Voltage[2]................................–0.5V to VCC + 0.5VOutput Current into Outputs (LOW).............................20 mAStatic Discharge Voltage.......................................... > 2001V(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
RangeCommercialIndustrial
Ambient Temperature
VCC
0°C to +70°C 3.3V ±300 mV–40°C to +85°C 3.3V ±300 mV
....–0.5V to +4.6V
DC Voltage Applied to Outputs
in High-Z State[2]....................................–0.5V to VCC + 0.5V
Electrical Characteristics Over the Operating Range
7C1399D-10
ParameterVOHVOLVIHVILIIXIOZIOSICCISB1ISB2
Description
Output HIGH VoltageOutput LOW VoltageInput HIGH VoltageInput LOW Voltage[2]Input Load CurrentOutput Leakage CurrentVCC Operating Supply Current
Automatic CE Power-down Current — TTL InputsAutomatic CE Power-down Current — CMOS Inputs[4]
GND ≤ VI ≤ VCC, Output DisabledVCC = Max., IOUT = 0 mA, f = fMAX = 1/tRCMax. VCC, CE ≥ VIH,
VIN ≥ VIH, or VIN ≤ VIL,f = fMAX
Output Short Circuit Current[3]VCC = Max., VOUT = GND
Test Conditions
VCC = Min., IOH = –4.0 mAVCC = Min., IOL = 8.0 mA
2.0–0.3–1–1Min.2.4
0.4VCC +0.3V0.8+1+1–3006010
L
103.01.2
2.0–0.3–1–1
Max.
7C1399D-12Min.2.4
0.4VCC +0.3V0.8+1+1–3005010103.01.2
7C1399D-15
ParameterVOHVOLVIHVILIIXIOZIOSICCISB1ISB2
Description
Output HIGH VoltageOutput LOW VoltageInput HIGH VoltageInput LOW VoltageInput Load CurrentOutput Leakage CurrentVCC Operating Supply CurrentAutomatic CE Power-Down Current — TTL InputsAutomatic CE Power-Down Current — CMOS Inputs[4]
GND ≤ VI ≤ VCC, Output DisabledVCC = Max., IOUT = 0 mA, f = fMAX = 1/tRCMax. VCC, CE ≥ VIH,
VIN ≥ VIH, or VIN ≤ VIL, f = fMAX
L
Output Short Circuit Current[3]VCC = Max., VOUT = GND
Test Conditions
VCC = Min., IOH = –4.0 mAVCC = Min., IOL = 8.0 mA
2.0–0.3–1–1Min.2.4
0.4VCC+0.3V0.8+1+1–3004010103.01.2Max.
UnitVVVVµAµAmAmAmAmAmAmA
Max.
UnitVVVVµAµAmAmAmAmAmAmA
Max. VCC, CE ≥ VCC – 0.3V, VIN ≥ VCC – 0.3V, or VIN ≤ 0.3V,
L
WE ≥VCC – 0.3V or WE ≤0.3V, f=fMAX
Max. VCC, CE ≥ VCC–0.3V, VIN ≥ VCC – 0.3V, or VIN ≤ 0.3V, WE≥VCC–0.3V or
L
WE≤ 0.3V, f=fMAX
Notes:
2.VIL (min.) = –2.0V and VIH(max) = VCC + 2V for pulse durations of less than 20 ns.
3.Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.4.Device draws low standby current regardless of switching on the addresses.
5.Tested initially and after any design or process changes that may affect these parameters.
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PRELIMINARY
Capacitance[5]
CY7C1399D
Max.566
UnitpFpFpF
ParameterCIN: AddressesCIN: ControlsCOUT
Description
Input CapacitanceOutput Capacitance
Test Conditions
TA = 25°C, f = 1 MHz, VCC = 3.3V
Thermal Resistance[5]
ParameterΘJAΘJC
Description
Thermal Resistance (Junction to Ambient)[5]Thermal Resistance (Junction to Case)[5]
Test Conditions
Still Air, soldered on a 3 × 4.5 inch, two-layer printed circuit board
All – Packages
TBDTBD
Unit°C/W°C/W
AC Test Loads and Waveforms
10-ns Device
OUTPUT
50Ω
* CAPACITIVE LOAD CONSISTSOF ALL COMPONENTS OF THETEST ENVIRONMENT
1.5V
Z = 50Ω
12-ns Device
R1 317Ω
30 pF*
3.3VOUTPUT
30pF
R2351Ω
(a)
Equivalentto:
THÉVENIN EQUIVALENT
167Ω
OUTPUT
1.73V
INCLUDINGJIG ANDSCOPE
(b)
High-Z characteristics:
R1317Ω
3.3V
ALL INPUT PULSES
3.0VGND
10%
90%
90%10%
≤3ns
OUTPUT
5 pF
INCLUDINGJIG ANDSCOPE(c)
R2
351Ω
≤3ns
(d)
Switching Characteristics Over the Operating Range[7]
1399D-10
ParameterRead Cycletpower[6]tRCtAAtOHAtACEtDOEtLZOEtHZOEtLZCE
VCC(typical) to the first accessRead Cycle TimeAddress to Data Valid
Data Hold from Address ChangeCE LOW to Data ValidOE LOW to Data ValidOE LOW to Low Z[8]OE HIGH to High Z[8, 9]CE LOW to Low Z[8]30
5
3
3
105
0
5
3
10010
10
3
125
0
6
10012
12
3
156
10015
15
µsnsnsnsnsnsnsnsns
Description
Min.
Max.
1399D-12Min.
Max.
1399D-15Min.
Max.
Unit
Notes:
6.tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed.
7.Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and capacitance CL = 30 pF.
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PRELIMINARY
Switching Characteristics Over the Operating Range (continued)[7]
1399D-10
ParametertHZCEtPUtPD
Write Cycle[10, 11]tWCtSCEtAWtHAtSAtPWEtSDtHDtHZWEtLZWE
Write Cycle TimeCE LOW to Write EndAddress Set-Up to Write EndAddress Hold from Write EndAddress Set-Up to Write StartWE Pulse Width
Data Set-Up to Write EndData Hold from Write EndWE LOW to High Z[10]WE HIGH to Low Z[8]3108700750
7
3128800870
7
3151010001080
7
nsnsnsnsnsnsnsnsnsns
Description
CE HIGH to High Z[8, 9]CE LOW to Power-UpCE HIGH to Power-Down
0
10
Min.
Max.5
0
12
1399D-12Min.
Max.6
0
15
1399D-15Min.
Max.7
Unitnsnsns
CY7C1399D
Notes:
8.At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.9.tHZOE, tHZCE, tHZWE are specified with CL = 5 pF as in AC Test Loads. Transition is measured ±200 mV from steady state voltage.
10.The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a
write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.11.The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05467 Rev. *CPage 5 of 10
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PRELIMINARY
CY7C1399D
Conditions
Min.2.0
Max.31.2
0tRC
UnitVmAmAnsns
Data Retention Characteristics (Over the Operating Range)
ParameterVDRICCDRtCDR [5]tR[12]
Description
VCC for Data Retention
Data Retention CurrentNon-L, Com’l / Ind’lL-Version Only
Chip Deselect to Data Retention TimeOperation Recovery Time
VCC = VDR = 2.0V,CE > VCC – 0.3V,VIN > VCC – 0.3V orVIN < 0.3VData Retention Waveform
DATA RETENTION MODE
VCCCE
3.0VtCDR
VDR>2V
3.0VtR
Switching Waveforms
Read Cycle No. 1[13, 14]
tRC
ADDRESS
tOHA
DATA OUT
PREVIOUS DATA VALID
tAA
DATA VALID
Read Cycle No. 2[14, 15]
CE
tACE
OE
tDOE
DATA OUT
tLZOE
HIGH IMPEDANCE
tLZCE
VCCSUPPLYCURRENT
tPU
50%
DATA VALID
tPD
ICC
50%
ISB
tHZOEtHZCE
tRC
HIGH IMPEDANCE
Notes:
12.Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 µs or stable at VCC(min.) > 50 µs.13.Device is continuously selected. OE, CE = VIL.14.WE is HIGH for read cycle.
15.Address valid prior to or coincident with CE transition LOW.
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PRELIMINARY
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled)[10, 16, 17]
tWC
ADDRESS
CE
tAW
WE
tSA
tPWE
tHA
CY7C1399D
OE
tSD
DATA I/O
NOTE 18tHZOE
DATAINVALID
tHD
Write Cycle No. 2 (CE Controlled)[10, 16, 17]
tWC
ADDRESS
CE
tSA
tAW
WE
tSD
DATA I/O
DATAINVALID
tHD
tHA
tSCE
Write Cycle No. 3 (WE Controlled, OE LOW)[11, 17]
tWC
ADDRESS
CE
tAW
WE
tSA
tHA
tSD
DATA I/O
NOTE 18
tHZWE
Notes:
16.Data I/O is high impedance if OE = VIH.
17.If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.18.During this period, the I/Os are in the output state and input signals should not be applied.
tHD
DATAINVALID
tLZWE
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PRELIMINARY
Truth Table
CEHLLL
WEXHLH
OEXLXH
Input/OutputHigh ZData OutData InHigh Z
Mode
Deselect/Power-DownReadWrite
Deselect, Output Disabled
Power
Standby (ISB)Active (ICC)Active (ICC)Active (ICC)
CY7C1399D
Ordering Information
Speed(ns)10
Ordering Code
CY7C1399D-10VXCCY7C1399D-10ZXCCY7C1399DL-10VXCCY7C1399DL-10ZXCCY7C1399D-10VXICY7C1399D-10ZXICY7C1399DL-10VXICY7C1399DL-10ZXI
12
CY7C1399D-12VXCCY7C1399D-12ZXCCY7C1399DL-12VXCCY7C1399DL-12ZXCCY7C1399D-12VXICY7C1399D-12ZXICY7C1399DL-12VXICY7C1399DL-12ZXI
15
CY7C1399D-15VXCCY7C1399D-15ZXCCY7C1399DL-15VXCCY7C1399DL-15ZXCCY7C1399D-15VXICY7C1399D-15ZXICY7C1399DL-15VXICY7C1399DL-15ZXI
PackageNameV21Z28V21Z28V21Z28V21Z28V21Z28V21Z28V21Z28V21Z28V21Z28V21Z28V21Z28V21Z28
Package Type
28-Lead Molded SOJ (Pb-Free)
28-Lead Thin Small Outline Package (Pb-Free)28-Lead Molded SOJ (Pb-Free)
28-Lead Thin Small Outline Package (Pb-Free)28-Lead Molded SOJ (Pb-Free)
28-Lead Thin Small Outline Package (Pb-Free)28-Lead Molded SOJ (Pb-Free)
28-Lead Thin Small Outline Package (Pb-Free)28-Lead Molded SOJ (Pb-Free)
28-Lead Thin Small Outline Package (Pb-Free)28-Lead Molded SOJ (Pb-Free)
28-Lead Thin Small Outline Package (Pb-Free)28-Lead Molded SOJ (Pb-Free)
28-Lead Thin Small Outline Package (Pb-Free)28-Lead Molded SOJ (Pb-Free)
28-Lead Thin Small Outline Package (Pb-Free)28-Lead Molded SOJ (Pb-Free)
28-Lead Thin Small Outline Package (Pb-Free)28-Lead Molded SOJ (Pb-Free)
28-Lead Thin Small Outline Package (Pb-Free)28-Lead Molded SOJ (Pb-Free)
28-Lead Thin Small Outline Package (Pb-Free)28-Lead Molded SOJ (Pb-Free)
28-Lead Thin Small Outline Package (Pb-Free)
IndustrialIndustrialCommercialIndustrialIndustrialCommercialIndustrialIndustrialOperatingRangeCommercial
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
Document #: 38-05467 Rev. *CPage 8 of 10
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PRELIMINARY
CY7C1399D
Package Diagrams
28-Lead(300-Mil)MoldedSOJV21
51-85031-B
28-Lead Thin Small Outline Package Type 1 (8x13.4 mm) Z28
51-85071-*G
All product and company names mentioned in this document may be the trademarks of their respective holders.Document #: 38-05467 Rev. *C
Page 9 of 10
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the useof any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to beused for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize itsproducts for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypressproducts in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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PRELIMINARY
Document History Page
Document Title: CY7C1399D 256K (32K x 8) Static RAM (Preliminary)Document Number: 38-05467REV.***A*B*C
Ecn No.201560233722262950307594
Issue DateSee ECNSee ECNSee ECNSee ECN
Orig. of ChangeSWIRKFRKFRKF
Description of Change
Advance Information data sheet for C9 IPP
DC parameters are modified as per EROS (Spec # 01-2165)Pb-free offering in the ‘ordering information
Added Tpower Spec in Switching Characteristics tableShaded Ordering Information
Reduced Speed bins to -10, -12 and -15 ns
CY7C1399D
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