STI5500_

FNOCENHANCED 32-BIT VL-RISC CPULASET TOP BOX / DVD BACKEND DECODERITNIDEWITH INTEGRATED HOST PROCESSORSUMMARYSTi5500....

-FAST INTEGER/BIT OPERATION ANDVERY HIGH CODE DENSITY

HIGH PERFORMANCE MEMORY/CACHESUBSYSTEM

-2KBYTES INSTRUCTION CACHE, 2KBYTESSRAM, 2KBYTES DATA CACHE/SRAM-160MBYTES/S BANDWIDTH

COMBINED VIDEO AND AUDIO DECODER CORE-VIDEO DECODER FULLY SUPPORTSMPEG-2 MP@ML

-MEMORY REDUCTION - PAL MP@ML IN12MBITS

-2 TO 8 BIT PER PIXEL OSD OPTIONS-LETTERBOX (16:9) DISPLAY FORMAT-HORIZONTAL AND VERTICAL RESIZINGFUNCTIONS

-AUDIO DECODER SUPPORTS LAYERS1 AND 2 OF MPEG, INTERFACE TO EXTERNAL DOLBY AC-3™ DECODERPAL/NTSC ENCODER

-MACROVISION™ VERSION 7.01/6.1COMPATIBLE

-TELETEXT, AND CLOSED CAPTION

-SIMULTANEOUS OUTPUT OF RGB, CVBSAND COMPONENT VIDEO

HIGH PERFORMANCE SDRAM MEMORYINTERFACE

-SUPPORTS 1 OR 2 16MBIT 100MHz SDRAMS-ACCESSIBLE BY MPEG DECODER, CPUAND DMAS

-HIGH BANDWIDTH ACCESS FROM CPUALLOWS HIGH PERFORMANCE OSDOPERATIONS

PROGRAMMABLE MEMORY INTERFACE-4 BANKS EACH 8/16 BITS WIDE

-SUPPORT FOR MIXED MEMORY,PERIPHERALS, DRAM AND POWER PCLINK INTERFACE-SERIAL INPUT

-SUPPORTS DSS, DVB, AND DVDBITSTREAMS

-32 PIDS SUPPORTED

.....

-DES AND DVB DESCRAMBLERS-32 SI/PSI FILTERS OF 16 BYTESVECTORED INTERRUPTS - 8 PRIORITIZEDLEVELS

DMA ENGINES/INTERFACES

-2 UARTS, 1 I2C CONTROLLER, 3 PWMOUTPUTS, 3 TIMERS, 3 CAPTURE TIMERS-24 BITS OF PIO SHARED WITH SERIALINTERFACES

-OS LINK INTERFACE

-BLOCK MOVE DMA, 2 MPEG DMAS-TELETEXT INTERFACE

PROFESSIONAL TOOLSET SUPPORT-ANSI C COMPILER AND LIBRARIES

-INQUEST ADVANCED DEBUGGING TOOLSNON-INTRUSIVE DEBUG CONTROLLER-HARDWARE BREAKPOINTS-REAL TIME TRACE208 PIN PQFP PACKAGE

DESCRIPTION

The STi5500 is the first of a new generation ofintegrated multimedia decoder engines for set topbox and DVD applications. It offers a high level ofintegration by reducing the complete set top boxdecoding chain from Transport Demux toPAL/NTSC Encoder onto one chip. At the same timeit dramatically enhances CPU and Graphics per-formance, and cuts down total system memory cost.

PQFP208(Plastic Quad Flat Pack)ORDER CODE : STi5500October 1997

This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

1/11

STi5500NOT_TRSTDATA[15]158208207206205204203202201200199198197196195194193192191190189188187186185184183182181180179178177176175174173172171170169168167166165164163162161160159VDDPIO3[7]PIO2[0]GNDPIO2[3]PIO2[4]PIO2[5]PIO2[7]PIO1[0]PIO1[2]PIO1[5]PIO1[6]PIO1[7]PIO4[7]PIO0[0]PIO0[3]PIO0[4]VDDGNDPIO0[5]PIO0[6]PIO0[7]IRQ[0]IRQ[1]IRQ[2]BRM0BRM1BRM2NOT_RSTSDAV_CLK (PI394_CLK)SDAV_CLK (PI394_DATA)SDAV_DIR (PI394_CLK)OSC_INVDDGNDF_DATAF_B_BCLKF_P_CLKF_ERRNRSS_CLKNRSS_OUTNRSS_INPCM_CLKOUT (A_C_STB)PCM_DATA (A_C_DATA)PCM_CLKINLRCLK (A_WORD_CLK)A_C_REQA_PTS_STBVDDGNDNOTHSYNCODD_OR_EVEN12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152157156155154153152151150149148147146145144143142141140139138137136135134133132131130DATA[14]ADR[21]ADR[20]ADR[19]ADR[18]ADR[17]ADR[16]ADR[15]ADR[14]ADR[13]ADR[12]ADR[11]ADR[10]PIO3[6]PIO3[5]PIO3[4]PIO3[3]PIO3[2]PIO3[1]PIO3[0]PIO1[4]PIO1[3]PIO4[6]PIO4[5]PIO4[4]PIO4[3]PIO4[2]PIO4[1]PIO4[0]ADR[9]ADR[8]ADR[7]ADR[6]ADR[5]ADR[4]ADR[3]ADR[2]ADR[1]LAITI - PIN DESCRIPTIONNEDI.1 - Pin ConnectionsIFNCOGNDVDDGNDGNDGNDTDOTMSTCKTDIVDDVDDVDDDATA[13]DATA[12]DATA[11]DATA[10]DATA[9]DATA[8]GNDVDDDATA[7]DATA[6]DATA[5]DATA[4]DATA[3]DATA[2]DATA[1]DATA[0]GNDVDDN_PPC_MODCPU_CLK (PPC_CLK)READYNOT_CSDXXDMAXFERREADnotWRITENOT_CAS1GNDVDDNOT_CAS0NOT_RAS1NOT_RAS0NOT_CE3NOT_CE2NOT_CE1NOT_OENOT_WE1NOT_WE0GNDVDDPIXCLK_27MHzOSD_ACTIVEAUXCLKDQ[15]DQ[14]DQ[13]DQ[12]GNDVDDDQ[11]DQ[10]DQ[9]DQ[8]DQMUSTi5500PQFP208(Top View)129128127126125124123122121120119118117116115114113112111110109108107106105100101102VDD103GNDV_REF_DAC_RGI_REF_DAC_RGMEMCLKOUTB_OUTY_OUTGNDGNDV_REF_DAC_YCI_REF_DAC_YCGNDGNDNOT_SDRASNOT_SDCASNOT_SDCS[0]NOT_SDCS[1]NOT_SDWEMEMCLKINVDDA_0VDDA_1G_OUTR_OUTC_OUTCV_OUTVSSA_0VSSA_1DQMLAD[4]AD[5]AD[6]AD[7]AD[8]AD[9]AD[0]AD[1]AD[2]AD[3]DQ[0]DQ[1]DQ[2]DQ[3]DQ[4]DQ[5]DQ[6]AD[10]AD[11]DQ[7]VDDVDDVDDVDD10453545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798992/11

5500-01.EPSSUPPLIES1, 18, 34, 49, 67, 75, 86, 95,VDD102, 110, 119, 130, 139,149, 159, 171, 184, 2084, 19, 35, 50, 68, 77, 87, 96,GND103, 111, 120, 131, 140,150, 160, 172, 185, 20053, 60VDDA54, 61VSSAVIDEO OUTPUT INTERFACE57R_OUT56G_OUT55B_OUT63C_OUT64CV_OUT62Y_OUT59I_REF_DAC_RGB66I_REF_DAC_YCC58V_REF_DAC_RGB65V_REF_DAC_YCC117OSD_ACTIVE118PIXCLK_27MHz51NOTHSYNC52ODD_OR_EVENAC-3/MPEG1-2 AUDIO OUTPUT INTERFACE43PCM_CLKOUT / A_C_STB44PCM_DATA / A_C_DATA45PCM_CLKIN46LRCLK / A-WORD_CLK47A_C_REQ48A_PTS_STBEXTERNAL INTERRUPTS23, 25, 24IRQ0-2PROGRAMMABLE I/O15, 16, 17, 20, 21, 22PIO-0 [0, 3-7]9, 10, 198, 199, 11, 12, 13PIO-1 [0, 2-7]3, 5, 6, 7, 8PIO-2 [0, 3-5,7]201-207, 2PIO-3 [0-7]191-197, 14PIO-4 [0-7]JTAG INTERFACE188TCK186TDI189TDO187TMS190NOT_TRSTSYSTEM USE28BRM227BRM1_OR_BOOTFROMROM2629116BRM0_OR_OSLINK_SELNOT_RSTAUXCLKLAITII - PIN DESCRIPTION (continued)NEDI.2 - Pin ListIFNCOPinSTi5500NameTypePower SupplyGroundFunctionAnalog Power Supply for DENCAnalog Ground for DENCOOOOOOIIIII/OII/OI/OOOI/OOIIII/OI/OI/OI/OI/OIIOIIOO/IO/IIORed OutputGreen OutputBlue OutputChroma OutputComposite Video OutputLuma OutputDAC Current ReferenceDAC Current ReferenceDAC Voltage ReferenceDAC Voltage ReferenceOSD ActiveSystem Clock InputHorizontal SyncVertical Sync(PCM Clock Out) or AC3 Data Strobe Data OutPCM Data Out or AC3PCM CLock In From VCXOLeft/Right Clock or AC3 Word ClockAC3 Data RequestAC3 Audio PTS StrobeExternal InterruptsGeneral Purpose IOGeneral Purpose IOGeneral Purpose IOGeneral Purpose IOGeneral Purpose IOTest ClockTest Data InputTest Data InputTest Mode SelectTest ResetModem Voltage ControlVCXO Control Audio BRM or BootfromromDuring ResetVCXO Control Video BRM or Configure OslinkPinsResetAuxilary Clock for Any Purpose3/11

STi5500PinNameTypeFunctionSDRAM INTERFACE78-81, 69, 70, 71, 72, 73,AD[0:11]OSDRAM Address Bus74, 82, 8392, 93, 94, 97, 98, 99, 100,DQ[0:15]I/OSDRAM Data (Lower Byte)101, 106, 107, 108, 109,112-115 84, 85NOT_SDCS0-1OSDRAM Chip Selects89NOT_SDCASOSDRAM CAS88NOT_SDRASOSDRAM RAS90NOT_SDWEOSDRAM Write Enable104MEMCLKINISDRAM Memory Clock Input76MEMCLKOUTOSDRAM Memory Clock Output91DQMLODQ Mask Enable (Lower)105DQMUODQ Mask Enable (Upper)ROM AND EXTERNAL MICROPROCESSOR161-170, 173-183ADR[1:21]I/OExternal Memory Address Bus141-148, 151-158DATA[0:15]I/OExternal Memory Data Bus128NOT_RAS1_OR_HOLDREQODRAM RAS or Bus Request to External Micro136READYOHold off External Micro133READNOTWRITE_OR_DMAACKI/ODRAM R/W Strobe or DMA Acknowledge fromExternal Micro121, 122NOT_WE[0:1]I/OWrite Enable of SRAM129NOT_CAS0_OR_HOLDACKO/IDRAM CAS or Bus Grant from External Micro132NOT_CAS1_OR_NOT_DMAREQODRAM CAS or DMA Request (Ready) toExternal Micro124-126NOT_CE[1:3]OChip Select for Banks 1 - 3135NOT_CSIChip Select to Access SDRAM137PPC_CLKIPower PC System Clock127NOT_RAS0_OR_NOT_CE4ODRAM RAS or Chip Select for Bank 0134DMAXFERIDMA Transfer Control from External Micro138NOT_PPC_MODEIPresence of Power PC123NOT_OEI/OOutput Enable of RAM / ROMSDAV INERFACE30SDAV_CLKI/OData Strobe / CLK31SDAV_DATAI/OData Line32SDAV_DIRODirection for Transmit Truefer Transmit, Pulsefor Receive33OSC_INI/O49.152MHz Crystal InputNRSS INTERFACE40NRSS_CLKONRSS Serial Clock42NRSS_ININRSS Serial Data Input41NRSS_OUTONRSS Serial Data OutputP1394 INTERFACE30P1394_CLKI/OData Strobe / CLK31P1394_DATAI/OData Line32P1394_P_CLKI/OPacket ClockLAITII - PIN DESCRIPTION (continued)NEDII.2 - Pin List (continued)IFNCO4/11

LAITII - BLOCK DIAGRAMNEDFigure 1 : General Block DiagramIFNCOST20 CPUBLOCK MOVEDMA2 MPEGDMAsINTERRUPTCONTROLLERSTi5500EMILINKINTERFACEMPEG AUDIODECODERAC-3 I/F2KINSTRUCTIONCACHE2SMARTCARDINTERFACES(ASC)2K DATACACHE AND2K SRAMMPEG VIDEODECODEROS LINK2 UART1 I2CPIO3 PWMDIAGNOSTICSCONTROLLERAND SYSTEMSERVICESPAL/NTSCENCODER5/11

5500-02.EPSTELETEXTINTERFACELAITIII - INTERNAL CIRCUIT DESCRIPTIONNEDA general block diagram for the STi5500 is shownIFis Figure 1.NCOThe performance offered by the ST20 32-bit micro-core allows the following operations to be per-formed in software :

1Device drivers for Video, Audio and Sub-pictureDecoders

2Audio/Video/Subpicture synchronisation3System management functions4Electronic program guide5Conditional access module

The use of a 32-bit CPU enables advanced graph-ics routines to be employed for on-screen displayfunctions, allowing fast turnaround system up-grades.

III.1 - The ST20 32-bit CPU

The ST20 micro-core family has been developed bySGS-THOMSON Microelectronics to provide thetools and building blocks to enable the developmentof highly integrated application-specific 32-bit de-vices at the lowest cost and fastest time to market.The ST20 macrocell library includes the ST20Cxfamily of 32-bit VL-RISC (variable length reducedinstruction set computer) micro-cores, embeddedmemories, standard peripherals, I/O, controllersand ASICs.

The STi5500 uses the ST20 macrocell library toprovide all of the dedicated hardware modulesrequired in a set top box or DVD system.These include :

-High performance internal SRAM and cache sub-system,

-I2C interfaces to other devices in the set top box,-UART serial I/O interface to modem and auxiliaryports,

-Interrupt controller for internal and external interrupts,-DMA to MPEG audio and video device(s),

-External memory interface supporting DRAM,EPROM and peripherals,

-PWM/timer module for control of system clock VCXOs,-Programmable I/O pins,-Smart card interfaces.

III.2 - MPEG-2 Video/Audio Decoder

The video decoder implemented in the STi5500uses a patented memory reduction/bandwidth re-duction scheme to offer the user the best band-width/memory size compromise.

The algorithm is lossless and uses \"on-the-fly\"decoding to reduce the memory requirements to2 frame buffers in memory size reduction mode.When used in bandwidth reduction mode the mem-6/11

STi5500ory usage is the normal three buffers but the band-width required by the decoder is significantly re-duced over a classical implementation.In summary the features of this decoder core are :-Video decoder fully supports MPEG-2 Main Pro-file/Main Level (MP@ML),

-Memory reduction architecture allows sharing ofsingle 16MBit SDRAM between MPEG decoding,micro and transport functions - memory expand-able to 32Mbits of SDRAM,-Letterbox filter,

-Horizontal and vertical image re-sizing,

-2 to 8 bit OSD (6-bit luma resolution, 4-bit chromaresolution),

-Accepts MPEG-2 Program Streams, PES andMPEG-1 system streams,-Automatic error concealment.

The output from the video decoder is fed directly toa PAL/NTSC encoder unit generating simultane-ously a composite video signal, component Y/Cand RGB for each of the two standards.

The signals can be optionally encoded followingthe MacrovisionTM 7.01/6.1 specification if the userhas a licence to use the technology. The digitalencoder cell is also capable of encoding into thecomposite signal teletext and closed caption infor-mation.

The audio decoder performs MPEG levels 1 andII decoding and is functionally equivalent to theSTi3520A audio decoder. The STi5500 has a dedi-cated interface to an external Dolby AC3 decoderwhilst allowing audio buffering to be performed inthe 16 Mbit SDRAM.

III.3 - High Quality Graphics

The graphics performance of the STi5500 supportsthe new requirements for intelligent programguides and interactive applications.

The display interface supports up to 256 colours foreach OSD region and a transparency feature al-lows mixing of video with the OSD. Fast accessgraphics and many other additional features areavailable and are supported by a graphics library.Excellent system performance is obtained byclosely coupling the high performance RISC proc-essor and cache with the MPEG audio/video coreand display memory.

Low latency RISC access and DMA engines allowrapid construction of bit maps. DVD graphics arealso supported by an integrated sub picture de-coder. Pan and scan and letterbox output are pro-vided for 16:9 applications.

LAIT(continued)III - INTERNAL CIRCUIT DESCRIPTION NEDIII.4 - External MemoryIFNand data memory. The processor can access mem-The STi5500 has been designed to minimize sys-OCory via the general purpose External Memory Inter-tem costs. The external memory interface containsa zero glue logic DRAM controller and a low-cost16-bit EPROM interface.

The STi5500 applies a unique memory architecturewhich consolidates the system, on-screen display,audio and video memory into a single memory chip.Moreover, a patented memory management algo-rithm allows the STi5500 to decode an MPEG2 MP@ ML bitstream with CCIR601 NTSC pictures inonly 10.5 Mbits and with CCIR601 PAL pictures inonly 12MBits, with absolutely no impact on thepicture quality.

If 16MBits SDRAM is attached to the STi5500, then4 Mbits or more are free for other purposes suchas full screen high resolution graphics and proces-sor use. A second optional 16Mbit SDRAM can alsobe added for applications which require moregraphics features such as full screen still imagedisplay or processor memory.

The STi5500 also has a generic processor inter-face allowing DMA access to the SDRAM memoryby an external processor.

The SDRAM memory interface directly supports100MHz SDRAMs providing the very high band-widths to support MPEG decoding and display,OSD drawing and display, and general system use.Furthermore, the ST20 VL-RISC micro-core hasthe highest code density of any 32-bit CPU, leadingto the lowest cost program ROM.

III.5 - STi5500 Functional DescriptionIII.5.1 - STi5500 Functional Modules

Figure 1 shows the subsystem modules that com-prise the STi5500. These modules are outlinedbelow and more detailed information is given in thefollowing chapters of this datasheet.

III.5.2 - CPU

The Central Processing Unit (CPU) on the STi5500is the ST20-C2 32-bit processor core. It containsinstruction processing logic, instruction and datapointers and an operand register. It directly ac-cesses the high speed on-chip SRAM memory,which can store data or programs, and uses theCaches to reduce access time to off chip program

STi5500face (EMI) or via the SDRAM EMI which is sharedwith the MPEG decoder.

III.5.3 - Memory Subsystem

The STi5500 on-chip SRAM memory system pro-vides 160Mbytes/s internal data bandwidth, sup-porting pipelined 2-cycle internal memory accessat 25 ns cycle times. The STi5500 memory systemconsists of 2 Kbytes of SRAM, 2Kbytes of instruc-tion cache, a 2Kbyte data cache that can be pro-grammed to be SRAM, and an external memoryinterface (EMI).

The STi5500 product has 2 Kbytes of on-chipSRAM. The advantage of this is the ability to storetime critical code on chip, for instance interruptroutines, software kernels or device drivers, andeven frequently used data without these beingflushed from the caches.

The instruction and data caches are direct mappedwith a write-back system for the data cache andsupport burst accesses to the external memoriesfor refill and write-back which are effective for in-creasing performance with page-mode andSDRAM memories.

The STi5500 EMI controls access to the externalmemory and peripherals while the SDRAM EMIprovides access to the SDRAM buffer for theMPEG decoders, ST20 and DMA peripherals.The STi5500 EMI can access a 16 Mbyte (orgreater if DRAM is used) physical address spacein each of the four general purpose memory banks,and provides sustained transfer rates of up to80Mbytes/s.

Peripherals that support an asynchronous dataacknowledge are supported as is an externalPowerPC which can share the bus with theSTi5500 and access the SDRAM buffer throughthe device.

High memory bandwidths up to 200Mbytes/s canbe supported by the SDRAM EMI (see Figure 2).The STi5500 internal memory interconnect providesbuffering and arbitration of memory access requests tosustain very high throughput of memory accesses. Figure 1 STi5500 architectural block diagram.

7/11

LAIT(continued)III - INTERNAL CIRCUIT DESCRIPTION NEDFigure 2 : STi5500 Top-Level ArchitectureIFNOCCPU ARBITORI - CACHESRAMD - CACHESTi5500LINK INTERFACESDRAM ARBITORSDRAMAUDIOVIDEODENCCOMPRESSED DATA/REGISTER BUSCPUST-20ARBITORDRAMST-20 EMIROMSRAMCENTRAL COMMAND PORTPWMI2CUARTMPEG DMABLOCK MOVE DMAMPEG DMAPERIPHERAL DMACOMMUNICATIONSARBITOR5500-03.EPSIII.5.4 - System services module

The STi5500 system services module includes :-phase locked loop (PLL) - accepts 27MHz inputand generates all the internal high frequencyclocks needed for the CPU and the OS-Link. -Test access port - JTAG compatible,

-Diagnostics controller accessed via the JTAGport providing :

-Bootstrapping during development,-Hardware breakpoint and watchpoint,-Real time trace,

-External LSA triggering support.

III.5.5 - Serial Communications

To facilitate the connection of this system the frontend device and other peripherals, two UARTs(ASCs) are included in the device. The UARTsprovide an asynchronous serial interface. TheUART can be programmed to support a range ofbaud rates and data formats, for example, datasize, stop bits and parity. Two synchronous serialcommunications (SSC) interfaces are provided onthe device. These can be used for a remote controldevice for example via an I2C or SPI bus.III.5.6 - Interrupt Subsystem

The STi5500 interrupt subsystem supports eightprioritized interrupt levels. Four external interruptpins are provided. Level assignment logic allowsany of the internal or external interrupts to be as-signed and, if necessary, share any interrupt level.

8/11

III.5.7 - Link Interface

The link interface is an integrated transport streamprocessor which accepts either DSS or DVBstreams on a serial interface with a front-end de-vice. The interface performs the demultiplexingoperations with no interaction from the ST20. Insummary the features of the interface are :

-Framing of transport packets (SYNC byte detection),-PID filtering of up to 32 PIDs,

-Descrambling to DVB/DES standard - transportor PES level (DVB),

-Adaptation field parsing - detection and timestamping. System time clock adjustment handledby software.

-Section filtering - 32 filters,

-Demultiplexing of transport stream by PID,

-DMA and buffering of streams in memory withcommunication to CPU of buffer state,

-DMA of two of the streams to the audio and videoMPEG decoder compressed data FIFOs.In addition to these transport device functions theinterface can copy the entire transport stream orselected PIDs from the transport stream through anSDAV (high speed bi-directional serial bus) interface.Communication with the ST20 is made via inter-rupts and a shared memory space. The ST20 canplace filter values, DMA destinations and descram-bling keys, for example, in the shared memory tobe picked up later during demultiplexing/descram-bling operations.

LAIT(continued)III - INTERNAL CIRCUIT DESCRIPTION NEDOne dedicated to the ST20 called the ST20 EMI,III.5.8 - PWM and Counter ModuleIFNthis interface can support directly SRAM, DRAM,This unit includes three separate pulse widthOROM and FLASH and a second interface which isCmodulator (PWM) generators using a sharedused by the MPEG decoders (audio and video) andcounter, and three timer compare and capturechannels sharing a second counter.

The counters can be clocked from a pre-scaledinternal clock or from a pre-scaled external clockvia the capture clock input and the event on whichthe timer value is captured is also programmable.The PWM counters are 8-bit with 8-bit registers to setthe output high time. The capture/compare counterand the compare and capture registers are 32-bit.

STi5500III.5.9 - Parallel Programmable IO Module

Forty bits of parallel IO are provided. Each bit isprogrammable as an output or an input. The outputcan be configured as a totem pole or open draindriver. Input compare logic is provided which cangenerate an interrupt on any change on any input bit.Many pins of the STi5500 device are multi-functionand can either be configured as PIO or connectedto an internal peripheral signal.

III.5.10 - MPEG Video Decoder

The video decoder is a real-time video compressionprocessor supporting the MPEG-1 and MPEG-2standards at video rates up to 720 x 480 x 60 Hz and720 x 576 x 50 Hz. Picture format conversion for displayis performed by vertical and horizontal filters. User-de-fined bitmaps may be superimposed on the displaypicture through use of the on-screen display function.III.5.11 - PAL/NTSC encoder

The digital encoder which is integrated in the STi5500produces, from a multiplexed 4:2:2 YUV streamsimultainious RGB,CVBS and component outputson two triple DACs. The encoder can also performcloased-caption, CGMS or teletext encoding andallows MacrovisionTM 7.01/6.1 copy protection.III.5.12 - MPEG-1 Audio Decoder

The audio decoder is a fully compliant MPEG-1decoder (Layers 1 & 2)

III.6 - STi 5500 Internal Architecture and DataflowReference is made to the STi5500 internal archi-tecture block diagram, figure 2 in this section.The intention of the OMEGA architecture is to allowas much flexibility as possible for a user to designa memory system and arrange data in a mannerwhich best fits the system needs. There are twomain memory systems.

supports only SDRAM. An important architecturalfeature of the device is that the SDRAM memorycan be viewed by the ST20 as an extension of it’sown memory system. The ST20 memory arbitorcan make requests into the SDRAM arbitor whichare treated as the highest priority. A mechanism isimplemented to ensure that the microprocessorcannot block out completely the MPEG decoderform the SDRAM.

The STi 5500 device is divided into essentially twomain parts. The CPU system and peripherals andthe MPEG video/audio decoder system. The wholesystem is built around four interconnected arbitors.-The CPU arbitor,

-The Comunications (DMA) arbitor),-The ST20 arbitor,-The SDRAM arbitor.

Starting at the lowest level the CPU arbitor sched-ules outgoing requests to the memory system com-ing from the cache refil controller with the incomingrequests from the ST20 arbitor to the internalSRAM.

The communications arbitor schedules all the re-quests for access to the ST20 arbitor and conse-quently the memory system coming from the DMAengines. The CPU and the communications arbi-tors consequently make requests into the the ST20arbitor and are scheduled along with the requestsfrom the front-end interface in the following priority :-Link Interface - Highest priority,

-CPU arbitor - round robin with communicationsarbitor,

-Communications arbitor - round robin with CPUarbitor,

There are four possible destinations for these threerequestors :

-Shared Memory Interface (SDRAM),-Compressed data port,

-Register port ( for audio, video and DENC blocks),-ST20 external memory interface.

The ST20 arbitor works like a bus in that only oneaccess can be on-going at any one time, howevera split-transaction scheme allows tasks to bequeued at the receivers and allows the requestersto have multiple outstanding requests.

This means a transaction does not have to becomplete for another transaction to take place overthe arbitor. Hence, slow interfaces or transactionsdo not slow down the internal communications.

9/11

LAIT(continued)III - INTERNAL CIRCUIT DESCRIPTION NEDFor program specific information (EPG etc) thisThe ST20 arbitor can make two types of requestsIFNdata my be sent to an external buffer in SDRAM orinto SDRAM, a single word access (32-bits) or aOa memory on the external ST20 EMI.burst access of 4 x 32-bit words. The following tableCsummerizes the different types of accesses bysource and destination (see Table 1).

Data is moved around the device using a number

of general purpose DMA engines which are kickedoff by the CPU at a certain address and are thenautonomous. In a typical application data will arrivevia the front-end interface (a transport stream in aset-top application or a program / sector stream ina DVD application (see Table 1).

The link interface has a built in programmable DMAmultichannel engine which can be used to directthe data to any memory or memory mapped periph-eral. In the case of a set-top application a DMAdestination can be defined for each pid so foraudio/video (PES) data this destination would bethe compressed data FIFOs which are mapped intothe ST20 memory system at specific addresses.Table 1

SourceCPUCachesLink InterfaceDMA EnginesVideo DecoderAudio DecoderSMI/SDRAMSingle WordBurstBurst/SingleSingleLarge BurstsLarge BurstsST20 EMISingle WordBurstBurst/SingleSinglen/an/aInternal SRAMSingle WordSingle WordSingleSinglen/an/aCompressed Data/Reg. PortSingle Wordn/aSingleSinglen/an/aSTi5500In a DVD system the incoming sector stream datawould be sent, using the DMA in the front endinterface to a track buffer which could be either inexternal DRAM off the ST20 EMI or in sharedSDRAM. This is automatic and needs no CPUintervention appart from an initial configuration.The track buffer is then parsed in software and twogeneral purpose DMAs can be used to transferblocks of data from the track buffer to the com-pressed data FIFOs to be decoded. In a set-top boxapplication a transport stream can be split by pidinto many component streams.

The video/audio streams would be directly sent tothe CD fifos using a non-incremental DMA transfer.Other streams such as EPG data can be stored asa circular buffer in another memory space using anincremental DMA.

10/11

IV - PACKAGE MECHANICAL DATA : 208 PINS - PLASTIC QUAD FLAT PACKAA2Seating planeLAITNEDIFNCOPIN 1IDENTIFICATIONeSTi55000.10mmD3D1D0.004BA1CE3E1EL1KDimensionsRef.AA1A2BCDD1D3eEE1E3LL1KMin.0.253.200.170.09MillimetersTyp.Max.4.103.600.270.20Min.0.0100.1260.0070.004InchesTyp.Max.0.01610.1420.0110.0083.400.1340° (Min.), 7° (Max.)Note : Exact shape of each corner is optional.

This device is protected by US patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. The use ofMacrovision™’s copy protection technology in the device must be authorized by Macrovision™ and is intended for home and other limitedpay-per-view uses only, unless otherwise authorized in writing by Macrovision™. Reverse engineering or disassembly is prohibited. Pleasecontact your nearest SGS-THOMSON Microelectronics sales office for more information.

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibilityfor the consequences of use of such information nor for any infringement of patents or other rights of third parties which may resultfrom its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics.Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces allinformation previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in lifesupport decoders or systems without express written approval of SGS-THOMSON Microelectronics.

© 1997 SGS-THOMSON Microelectronics - All Rights Reserved

Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the PhilipsIC Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to

the I2C Standard Specifications as defined by Philips.

2

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - MoroccoThe Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.

11/11

PQFP208.TBL0.4530.6028.0025.500.5030.6028.0025.500.601.300.750.0181.2051.1021.0040.0201.2051.1021.0040.0240.0510.030PMPQF208.EPSL