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MITSUBISHI FLAT-BASE TYPEINSULATED PACKAGE INTERNAL FUNCTIONS BLOCK DIAGRAMRfo=1.5kΩNCFoVNCWNVN1VNUNWPVWPCVWP1VVPCVPVVP1VUPCUPVUP1RfoGndInFoVccGndInFoVccGndInFoVccGndInFoVccGndInFoVccGndInFoVccGndSi OutGndSi OutGndSi OutGndSi OutGndSi OutGndSi OutThNCNWVUPMAXIMUM RATINGS (Tj = 25°C, unless otherwise noted)INVERTER PARTSymbolVCES±IC±ICPPCTjParameterCollector-Emitter VoltageCollector CurrentCollector Current (Peak)Collector DissipationJunction TemperatureConditionVD = 15V, VCIN = 15VTC = 25°CTC = 25°CTC = 25°CRatings60075150255–20 ~ +150UnitVAAW°CCONTROL PARTSymbolVDVCINVFOIFOParameterSupply VoltageInput VoltageFault Output Supply VoltageFault Output CurrentConditionApplied between :VUP1-VUPCVVP1-VVPC, VWP1-VWPC, VN1-VNCApplied between :UP-VUPC, VP-VVPCWP-VWPC, UN • VN • WN-VNCApplied between :FO-VNCSink current at FO terminalRatings20202020UnitVVVmASep. 2001 元器件交易网www.cecb2b.com MITSUBISHI FLAT-BASE TYPEINSULATED PACKAGE TOTAL SYSTEMParameterSupply Voltage Protected byVCC(PROT)OC & SCVCC(surge)Supply Voltage (Surge)Module Case OperatingTCTemperatureStorage TemperatureTstgVisoIsolation VoltageSymbolConditionVD = 13.5 ~ 16.5V, Inverter Part,Tj = 125°C StartApplied between : P-N, Surge value or without switching(Note-1)60Hz, Sinusoidal, Charged part to Base, AC 1 min.Ratings400500–20 ~ +100–40 ~ +1252500UnitVV°C°CVrms(Note-1) Tc measurement point is as shown below. (Base plate depth 3mm)PBTTHERMAL RESISTANCESSymbolParameterTest ConditionMin.—————LimitsTyp.—————Max.0.491.380.300.470.027UnitRth(j-c)QInverter IGBT part (per 1 element), (Note-1)Junction to case ThermalInverter FWDi part (per 1 element), (Note-1)Rth(j-c)FResistancesRth(j-c’)QInverter IGBT part (per 1 element), (Note-2)Rth(j-c’)FInverter FWDi part (per 1 element), (Note-2)Case to fin, Thermal grease applied (per 1 module)Rth(c-f)Contact Thermal Resistance(Note-2)TC measurement point is just under the chips.If you use this value, Rth(f-a) should be measured just under the chips.ELECTRICAL CHARACTERISTICS (Tj = 25°C, unless otherwise noted)INVERTER PARTSymbolVCE(sat)VECtontrrtc(on)tofftc(off)ICESParameterCollector-EmitterSaturation VoltageFWDi Forward VoltageTest ConditionVD = 15V, IC = 75A (Fig. 1)VCIN = 0V, Pulsed–IC = 75A, VD = 15V, VCIN = 15VVD = 15V, VCIN = 15V↔0VVCC = 300V, IC = 75ATj = 125°CInductive Load (upper and lower arm)VCE = VCES, VCIN = 15V(Fig. 4)Tj = 25°CTj = 125°C(Fig. 2)Min.———0.8——————LimitsTyp.1.71.72.21.20.150.42.40.6——Max.2.32.33.32.40.31.03.31.2110UnitVVSwitching TimeCollector-EmitterCutoff CurrentBPNWVU63mmTc°C/Wµs (Fig. 3)Tj = 25°CTj = 125°CmASep. 2001 元器件交易网www.cecb2b.com MITSUBISHI FLAT-BASE TYPEINSULATED PACKAGE CONTROL PART SymbolIDVth(ON)Vth(OFF)OCSCtoff(OC)OTOTrUVUVrIFO(H)IFO(L)tFO Parameter Circuit Current Input ON Threshold VoltageInput OFF Threshold VoltageOver Current Trip LevelShort Circuit Trip LevelOver Current Delay TimeOver Temperature ProtectionSupply Circuit Under-VoltageProtection Fault Output CurrentMinimum Fault Output PulseWidth Test Condition VD = 15V, VCIN = 15V VN1-VNCVXP1-VXPC Min.——1.21.7—192115——111—11.5———1.0 LimitsTyp.40131.52.0—226—2411011810012.012.5—101.8 Max.55181.82.3380320———125—12.5—0.0115— UnitmAVAAµs°CVmAms Applied between :UP-VUPC, VP-VVPC, WP-VWPC UN • VN • WN-VNC Tj = –20°C VD = 15V (Fig. 5,6)Tj = 25°C Tj = 125°C (Fig. 5,6)–20≤ Tj ≤ 125°C, VD = 15V VD = 15V(Fig. 5,6) Trip levelBase-plate Reset levelTemperature detection, VD = 15V Trip level –20 ≤ Tj ≤ 125°C Reset levelVD = 15V, VFO = 15VVD = 15V (Note-3)(Note-3) (Note-3)Fault output is given only when the internal OC, SC, OT & UV protection. Fault output of OT protection operate by lower arm.Fault output of OC, SC protection given pulse. Fault output of OT, UV protection given pulse while over level. MECHANICAL RATINGS AND CHARACTERISTICS Symbol——— Parameter Mounting torqueMounting torqueWeight Main terminalMounting part —Test Condition screw : M5screw : M5 Min.2.52.5— LimitsTyp.3.03.0560 Max.3.53.5— UnitN • mN • mg RECOMMENDED CONDITIONS FOR USE SymbolVCCVDVCIN(ON)VCIN(OFF)fPWMtdead Parameter Supply VoltageControl Supply VoltageInput ON VoltageInput OFF VoltagePWM Input FrequencyArm Shoot-throughBlocking Time Test Condition Applied across P-N terminals Applied between :VUP1-VUPC, VVP1-VVPC VWP1-VWPC, VN1-VNC(Note-4) Applied between :UP-VUPC, VP-VVPC, WP-VWPC UN • VN • WN-VNC Using Application Circuit input signal of IPM, 3φsinusoidal PWM VVVF inverter(Fig. 8)For IPM’s each input signals (Fig. 7) Recommended value ≤ 400 15±1.5≤ 0.8≥ 4.0≤ 20≥ 2.5 UnitVVVkHzµs (Note-4)Allowable Ripple rating of Control Voltage : dv/dt ≤ ±5V/µs, 2Vp-p Sep. 2001 元器件交易网www.cecb2b.com MITSUBISHI FLAT-BASE TYPEINSULATED PACKAGE PRECAUTIONS FOR TESTING1.Before appling any control supply voltage (VD), the input terminals should be pulled up by resistores, etc. to their corre-sponding supply voltage and each input signal should be kept off state.After this, the specified ON and OFF level setting for each input signal should be done.2.When performing “OC” and “SC” tests, the turn-off surge voltage spike at the corresponding protection operation should notbe allowed to rise above VCES rating of the device.(These test should not be done by using a curve tracer or its equivalent.)P, (U,V,W)IN(Fo)IN(Fo)P, (U,V,W)VCIN(0V)VIcVCIN(15V)V–IcVD (all)U,V,W, (N)VD (all)U,V,W, (N)Fig. 1 VCE(sat) TestFig. 2 VEC Test a) Lower Arm SwitchingPVCIN(15V)VCINSignal input(Upper Arm)Signal input(Lower Arm) FotrrU,V,WIrrCSVCEIc90%Vcc90%Nb) Upper Arm SwitchingVCINSignal input(Upper Arm)Signal input(Lower Arm) VD (all)PIc10%10%tc (on)10%tc (off)10%U,V,WVCINCSVcctd (on)trtd (off)tfVCIN(15V)Fo(ton= td (on) + tr)N(toff= td (off) + tf)VD (all)IcFig. 3 Switching time Test circuit and waveformP, (U,V,W)IN(Fo)AVCINPulseVCEVCIN(15V)Over CurrentVD (all)U,V,W, (N)ICtoff (OC)Constant CurrentOCFig. 4 ICES TestP, (U,V,W)IN(Fo)Short Circuit CurrentVCCICConstant CurrentSCVCINVD (all)U,V,W, (N)ICFig. 5 OC and SC TestFig. 6 OC and SC Test waveformPVDVCINPU,V,WVccVDVCINNNIcVCINP0VVCINN0VtttdeadtdeadtdeadFig. 7 Dead time measurement point exampleSep. 2001 元器件交易网www.cecb2b.com MITSUBISHI FLAT-BASE TYPEINSULATED PACKAGE P20k≥10µVUP1¡VccVDOUTSiUIFUPVUPC≥0.1µInGNDGNDVcc+–VVP1OUTSiVVDVPVVPCVWP1InGNDGNDVccMOUTSiWVD20kWPVWPCInGNDGNDVccOUT Si¡IF≥10µUN≥0.1µFoInGNDGNDNTEMP≥10µ20kTh¡IFVccVNFoInOUT Si≥0.1µ20kGNDGNDVN1≥10µ¡VccFoInOUT SiNCVDIFWN≥0.1µVNCGNDGNDNC5V1kFoRfo: Interface which is the same as the U-phaseFig. 8 Application Example CircuitNOTES FOR STABLE AND SAFE OPERATION ;Design the PCB pattern to minimize wiring length between opto-coupler and IPM’s input terminal, and also to minimize thestray capacity between the input and output wirings of opto-coupler.Quick opto-couplers: TPLH, TPLH ≤ 0.8µs. Use High CMR type. The line between opto-coupler and intelligent moduleshould be shortened as much as possible to minimize the floating capacitance.Slow switching opto-coupler: recommend to use at CTR = 100 ~ 200%, Input current = 8 ~ 10mA, to work in active.Use 4 isolated control power supplies (VD). Also, care should be taken to minimize the instantaneous voltage charge of thepower supply.Make inductance of DC bus line as small as possible, and minimize surge voltage using snubber capacitor between P and Nterminal.Use line noise filter capacitor (ex. 4.7nF) between each input AC line and ground to reject common-mode noise from AC lineand improve noise immunity of the system.••••••Sep. 2001 因篇幅问题不能全部显示，请点此查看更多更全内容