mmc接口（1）——emmc引脚驱动能力

EMMC IO Operation Mode

The EMMC IO PAD is a multipurpose PAD which can be programmed to operate in different
modes:
1、Output with predetermined source/ sink impedance
2、Open drain
3、Input
4、Tristate
5、Weak pull up or pull down
The PAD mode of operation is determined by ‘phyctrl_dren_xxx’, ‘phyctrl_oden_xxx’, ’phyctrl_ren_xxx’ and ‘phyctrl_pu_xxx’ control signal(xxx equals to dat or cmd).
The ‘phyctrl_dr_ty[2:0]’ are used to program the drive strength of the IO in push/pull mode of operation by programming the source/sink impedance of EMMC51 IO. The PAD source/sink impedance can be programmed to 50, 33, 66, 100 or 40 Ohms. The source/sink impedance variation across PVT exceeds 25 % of its nominal value. Trimming bits are provided to greatly reduce the variation. phyctrl_rtrim[3:0] control are used to trim the selected source/sink impedance value. The dynamic range of the trim is +/- 25%. The power on default setting of phyctrl_rtrim[3:0] equals 4’b1110.

所以我们需要关注：
1、phyctrl_dren_xxx, phyctrl_oden_xxx, phyctrl_ren_xxx and phyctrl_pu_xxx control signal
2、phyctrl_dr_ty[2:0]
3、phyctrl_rtrim[3:0]

IO的阻抗则由phyctrl_dr_ty[2:0]控制

相关文件
u-boot/drivers/mmc/rockchip_sdhci.c
kernel/drivers/phy/rockchip/phy-rockchip-emmc.c

uboot设置

#define RK_CLRSETBITS(clr, set)         ((((clr) | (set)) << 16) | (set))

rk3399_emmc_phy_power_on
	u32 phy_con6;
	phy_con6 = readl(&phy->emmcphy_con[6]);
	printf( "## [\e[31m%s\e[0m():%d] phy_con6=%x !!!!!! \n", __func__, __LINE__, phy_con6);
	//phy_con6=1108		0001000100001000	irom中的阻抗配置bit[6:4]为0

	writel(RK_CLRSETBITS(7 << 4, 0), &phy->emmcphy_con[6]);
	//01110000		将emmcphy_con[6]的bit[6:4]置为0，设置pad阻抗
	/*
         * According to the user manual, calpad calibration
         * cycle takes more than 2us without the minimal recommended
         * value, so we may need a little margin here
         */
	writel(RK_CLRSETBITS(1, 1), &phy->emmcphy_con[6]);
	/* Set the frequency of the DLL operation */
	writel(RK_CLRSETBITS(1 << 1, 1 << 1), &phy->emmcphy_con[6]);

rk3399_emmc_phy_power_off
	writel(RK_CLRSETBITS(1, 0), &phy->emmcphy_con[6]);
	writel(RK_CLRSETBITS(1 << 1, 0), &phy->emmcphy_con[6]);

irom默认配置：
phy_con5=0
phy_con2=3ff
phy_con3=1ff
phy_con6=110b		0001000100001011
phy_status=6c		0000000001101100

uboot修改的配置：
phy_con5=0
phy_con2=3ff
phy_con3=1ff
phy_con6=1108		0001000100001000
phy_status=1c		0000000000011100

内核设置

#define HIWORD_UPDATE(val, mask, shift) \
		((val) << (shift) | (mask) << ((shift) + 16))

#define PHYCTRL_DR_MASK                 0x7
#define PHYCTRL_DR_SHIFT                0x4
#define PHYCTRL_DR_50OHM                0x0
#define PHYCTRL_DR_33OHM                0x1
#define PHYCTRL_DR_66OHM                0x2
#define PHYCTRL_DR_100OHM               0x3
#define PHYCTRL_DR_40OHM                0x4

regmap_write(rk_phy->reg_base, rk_phy->reg_offset + GRF_EMMCPHY_CON6,
		HIWORD_UPDATE(PHYCTRL_DR_50OHM, PHYCTRL_DR_MASK, PHYCTRL_DR_SHIFT));

内核读到的配置：
phy_con5=0
phy_con2=3ff
phy_con3=1ff
phy_con6=110b		0001000100001011
phy_status=74		0000000001110100

内核设置的配置：
phy_con5=0
phy_con2=3ff
phy_con3=1ff
phy_con6=1108
phy_status=1c

可以看到phy_con6设置的io阻抗没有发生变化，其他的控制寄存器也没有发生变化，con6默认会“Enable retention mode——EMMCIOs will retain its input programming state during VCORE is off in sleep mode”
phyctrl_rtrim根据emmc的不同状态在发生变化。

硬件原理

EMMC_D0
EMMC_D1
EMMC_D2
EMMC_D3
EMMC_D4
EMMC_D5
EMMC_D6
EMMC_D7
EMMC_CMD
EMMC_CLKO
EMMC_STRB